Sr Principal Application Engineer

Key Responsibilities

• Lead adoption of AI-driven design and debug workflows (e.g., Innovus AI Assistant, agentic workflows)
• Apply AI/ML techniques to improve: Design debug efficiency, Flow automation, Design convergence and optimization
• Contribute to internal and customer-facing initiatives involving: LLM-based debug assistance, Knowledge-driven design automation, Multi-agent workflows for implementation and signoff
• Help define and evolve next-generation AE workflows leveraging AI capabilities
• Customer Engagement: Act as a trusted technical advisor to key customers, Deliver workshops, training, and best-practice guidance, including AI-enabled workflows, Drive issue resolution across AE, PE, and R&D teams, Build long-term strategic relationships with customer design teams
• Physical Design & Implementation: Drive end-to-end physical design closure including: Floorplanning, placement, CTS, routing, and optimization, Congestion, power, and performance tuning, Debug complex design issues and provide scalable solutions across blocks and full-chip designs, Optimize PPA (Performance, Power, Area) and turnaround time (TAT) using both traditional and AI-assisted approaches
• Timing Signoff & Correlation: Enable and support timing closure and signoff flows using industry-standard methodologies, Debug timing issues including: Setup/hold violations, Derates, variation modeling, and multi-corner/multi-mode analysis

Required Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related field
• Demonstrated experience in: AI/ML, data-driven workflows, or automation applied to engineering problems, Digital backend design (physical design / PnR), or EDA application engineering or CAD support
• Strong technical foundation in one or more of: Place-and-route (PnR) flows, Static timing analysis (STA) and timing closure methodologies
• Experience working with Innovus or comparable implementation tools
• Strong debugging, problem-solving, and communication skills in complex SoC designs

Preferred Qualifications

• Experience with AI/ML applications in EDA, including one or more of: AI-assisted design/debug (e.g., Innovus AI Assistant, JedAI), Workflow automation or data-driven optimization
• Experience with advanced nodes (≤7nm) and large-scale SoC or full-chip implementation
• Strong knowledge of timing signoff methodologies, including: MMC (Multi-Mode Multi-Corner), Variation modeling (SOCV, AOCV), Extraction and signoff correlation flows
• Hands-on experience with Cadence EDA tools (one or more strongly preferred): Innovus (PnR / Implementation), Tempus (STA / Signoff), Quantus (Extraction), Pegasus (Physical Verification), Genus (Synthesis)
• Prior experience in Application Engineering, CAD, or customer-facing roles