Senior/Staff Design Verification Engineer - Coherent Interconnect

About the role

The ARM Neoverse Coherent Mesh Network is a highly scalable, configurable system interconnect used in various applications including networking infrastructure, storage, server, high performance compute, AI, and industrial solutions. As a key member of the team, you will play a crucial role in developing and maintaining the next generation of products.

Responsibilities

• Build and maintain detailed verification plans and strategies
• Work alongside architects and designers to debug and develop new features, balancing the needs of multiple partners
• Architect and develop efficient SystemVerilog/UVM based test benches
• Design new stimulus and coverage, debug functional regression failures, and close coverage
• Develop and drive improvements in our verification methodology

Requirements

• Bachelor's, Master's or PhD in Electrical/Computer Engineering or Computer Science
• 7+ years of hands-on experience in verification/RTL design
• Experience with CPU microarchitecture including knowledge of cache coherence, memory systems, and bus protocols (e.g. AMBA CHI, ACE)
• Previous experience in specification, creation, and debug of System Verilog/UVM constrained-random testbenches

Nice to have

• Applied knowledge and experience in the areas of PCIe or Compute Express Link
• Experience in Formal Verification techniques or scripting languages such as Python or Perl

In Return

• Competitive salary range: $198,100-$268,000 per year
• Flexible working arrangements
• Equal opportunities and diversity
• Comprehensive benefits package

Pay

$198,100 - $268,000 per year

Schedule

Hybrid working is offered

Benefits

• Health and wellness programs
• Work-life balance initiatives
• Financial rewards
• Professional and personal development opportunities