Senior Staff Design Verification Engineer – Coherent Interconnect

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are enabling leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

Job Description

The Role: SiFive is looking for a Senior Staff Design Verification Engineer to lead verification of a next-generation cache-coherent interconnect subsystem used in high-performance SoCs. This is a Senior Staff individual-contributor role focused on defining verification strategy, identifying risk early, solving complex subsystem-level problems, and raising the quality bar across the broader verification effort.

• Own verification planning and execution for a scalable cache-coherent interconnect subsystem, from block-level verification through subsystem integration and signoff.

• Define verification strategy, test plans, environments, and closure criteria for coherent traffic, ordering rules, backpressure, flow control, quality-of-service behavior, and subsystem integration across multiple interfaces and bridge paths.

• Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models to validate complex interconnect and protocol behavior.

• Create high-value directed and constrained-random scenarios that expose corner cases in coherency, concurrency, credits, arbitration, QoS, and bandwidth-sensitive behavior.

• Partner closely with architecture, RTL, formal, and software teams to review specifications, close ambiguities early, and improve overall verification quality.

• Debug failures efficiently, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.

• Contribute to methodology and infrastructure improvements that benefit the broader horizontal interconnect verification effort, not just the block directly assigned to you.

• Mentor engineers and help raise verification quality across the team.

Minimum Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

• 8+ years of experience in ASIC or SoC design verification, with depth appropriate for a Senior Staff / T5 role.

• Strong hands-on experience with SystemVerilog and building reusable verification infrastructure for complex hardware subsystems.

• Strong understanding of cache-coherent systems, on-chip interconnects, memory subsystem behavior, and verification of ordering and flow-control semantics.

• Strong protocol knowledge in CHI, ACE, CXL, AXI, or similar coherent and high-performance interconnect standards.

• Experience creating test plans, assertions, coverage models, and debug workflows for complex hardware subsystems.

• Strong scripting and automation skills in Python or similar languages.

• Strong communication skills and the ability to work effectively across architecture, RTL, and verification teams in a fast-moving environment.

Preferred Qualifications

• Experience verifying coherent interconnect, cache, or memory-subsystem IP in high-performance SoCs.

• Experience with protocol-conversion or bridge-heavy subsystems.

• Experience with formal verification, performance-oriented verification, or emulation / FPGA-assisted debug.

• Demonstrated technical leadership and the ability to influence verification quality beyond immediate ownership.