Staff Design Verification Engineer – Coherent Interconnect

About SiFive

The pioneers of RISC-V, SiFive is revolutionizing compute by enabling the most advanced solutions in AI, ML, automotive, data center, mobile, and consumer markets. SiFive empowers leading tech companies to innovate and deliver solutions that make the world a better place.

Job Description

SiFive seeks a Staff Design Verification Engineer to lead the verification of a next-generation cache-coherent interconnect subsystem in high-performance SoCs. Key responsibilities include:

• Ownership of verification planning and execution for a scalable cache-coherent interconnect subsystem.
• Development and maintenance of robust verification environments, checkers, scoreboards, stimulus, and coverage models for coherent traffic, ordering rules, backpressure, flow control, and error handling.
• Verification of protocol adaptation and integration across multiple interface types and bridge paths, including conversion, buffering, deinterleaving, and related data movement behaviors.
• Driving verification of advanced interconnect behaviors such as QoS handling, arbitration policy, virtual-network behavior, and transport-level correctness.
• Definition of high-value directed and constrained-random test scenarios that expose corner cases in coherency, concurrency, ordering, credits, and integration.
• Collaboration with architecture, design, formal, and software teams to clarify requirements, close ambiguities early, and accelerate debug and signoff.
• Analysis of failures, isolation of root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
• Improvement of verification methodology, infrastructure, and productivity for the broader interconnect verification effort.
• Contribution to review quality across specs, verification plans, coverage closure, and debug strategy.

Minimum Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 7+ years of experience in ASIC or SoC design verification.
• Strong hands-on experience with SystemVerilog and UVM-based verification.
• Strong understanding of cache-coherent systems, on-chip interconnects, or memory-system verification.
• Experience verifying complex protocol behavior such as ordering, flow control, backpressure, buffering, arbitration, and error handling.
• Experience building reusable testbench components, assertions, coverage models, and debug infrastructure.
• Strong debugging skills and ability to root-cause issues across specification, RTL, and testbench layers.
• Ability to work effectively across architecture, design, and verification teams in a fast-moving environment.

Preferred Qualifications

• Experience with coherent interconnects, NoCs, memory fabrics, or large subsystem integration.
• Experience with one or more industry protocols such as AXI, CHI, CXL, UCIe, or similar high-performance interface standards.
• Experience with formal verification, performance-oriented verification, or emulation/FPGA-assisted debug.
• Experience verifying protocol-conversion or bridge-heavy subsystems.
• Familiarity with Python or other scripting languages used for DV infrastructure and automation.
• Experience mentoring other engineers and raising team-wide verification quality.