Senior Staff Design Verification Engineer – Coherent Interconnect

About SiFive

The pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by enabling leading technology companies to innovate, optimize, and deliver advanced solutions across various markets. SiFive’s compute platforms are pushing the boundaries of what’s possible, from artificial intelligence and machine learning to automotive, data center, mobile, and consumer applications. SiFive is proud to have been recognized as the Most Respected Private Company by the GSA four times. For more information, visit our website and Glassdoor pages.

Job Description

The Role: SiFive is seeking a Senior Staff Design Verification Engineer to lead the verification of a next-generation cache-coherent interconnect subsystem used in high-performance SoCs. This role focuses on defining verification strategy, identifying risks, solving complex subsystem-level problems, and enhancing overall verification quality.

• Own verification planning and execution: Develop and execute verification plans for a scalable cache-coherent interconnect subsystem, ensuring block-level verification extends to subsystem integration and sign-off.
• Define verification strategy: Create test plans, environments, and closure criteria for coherent traffic, ordering rules, backpressure, flow control, quality-of-service behavior, and subsystem integration across multiple interfaces and bridge paths.
• Create robust verification environments: Build and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models to validate complex interconnect and protocol behavior.
• Partner with cross-functional teams: Collaborate with architecture, RTL, formal, and software teams to review specifications, close ambiguities, and improve overall verification quality.
• Debug failures: Efficiently debug failures, isolate root causes, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
• Contribute to methodology and infrastructure improvements: Enhance verification methodologies and infrastructure to benefit the broader horizontal interconnect verification effort.
• Mentor engineers: Guide and mentor junior engineers to raise verification quality across the team.

Minimum Qualifications

• Education: BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Experience: 8+ years of experience in ASIC or SoC design verification, with depth appropriate for a Senior Staff / T5 role.
• Skills: Strong hands-on experience with SystemVerilog and building reusable verification infrastructure for complex hardware subsystems; strong understanding of cache-coherent systems, on-chip interconnects, memory subsystem behavior, and verification of ordering and flow-control semantics; strong protocol knowledge in CHI, ACE, CXL, AXI, or similar coherent and high-performance interconnect standards; experience creating test plans, assertions, coverage models, and debug workflows for complex hardware subsystems; strong scripting and automation skills in Python or similar languages; strong communication skills and ability to work effectively across architecture, RTL, and verification teams in a fast-moving environment.

Preferred Qualifications

• Experience: Experience verifying coherent interconnect, cache, or memory-subsystem IP in high-performance SoCs; experience with protocol-conversion or bridge-heavy subsystems; experience with formal verification, performance-oriented verification, or emulation/FPGA-assisted debug; demonstrated technical leadership and ability to influence verification quality beyond immediate ownership.

What Success Looks Like

• Verification plans: Complete, concrete, and aligned to real architectural risks.
• Bugs: Critical bugs found early, reproduced efficiently, and closed with durable fixes.
• Coverage and test quality: Meaningful improvement in coverage and test quality under your ownership.
• Verification effort: More scalable, predictable, and reusable verification effort due to your contributions.
• Technical partnership: Design and architecture teams rely on you as a strong technical partner for difficult verification and debug problems.

Additional Information

• Background and Reference Checks: Successful background and reference checks are required.
• E-Verify: This position is eligible for E-Verify and must provide proof of right to work in the United States of America.
• Benefits: Comprehensive, competitive benefits package including healthcare and retirement plans, paid time off, and more!