Staff Design Verification Engineer – Coherent Interconnect

About SiFive

The pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by enabling leading technology companies to innovate, optimize, and deliver advanced solutions across various markets. SiFive’s compute platforms are pushing the boundaries of what’s possible, from artificial intelligence and machine learning to automotive, data center, mobile, and consumer applications. SiFive is proud to have been recognized as the Most Respected Private Company by the GSA four times. For more information, visit our website and Glassdoor pages.

Job Description

SiFive is seeking a Staff Design Verification Engineer to drive the verification of a next-generation cache-coherent interconnect subsystem, with a particular focus on CXL-related protocol behavior, bridge paths, and subsystem integration. This role involves independent ownership of complex verification problems, defining robust verification plans, identifying risks early, and enhancing overall verification quality across the interconnect effort.

• Drive verification of subsystem behavior across interface boundaries, protocol adaptation layers, and bridge paths, with emphasis on CXL and related coherent interconnect flows.
• Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models for coherent traffic, ordering rules, backpressure, flow control, QoS, and error handling.
• Define high-value directed and constrained-random scenarios that expose corner cases in coherency, concurrency, ordering, credits, arbitration, latency-sensitive flows, and bandwidth-sensitive behavior.
• Partner closely with architecture, RTL, formal, and software teams to review specifications, close ambiguities early, and improve overall verification quality.
• Analyze failures efficiently, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
• Contribute reusable methodology, infrastructure, and automation improvements that benefit the broader horizontal interconnect verification effort, not just the block directly assigned to you.
• Mentor engineers and help raise verification quality across the team through reviews, technical guidance, and stronger verification practices.

Minimum Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 7+ years of experience in ASIC or SoC design verification, with strong hands-on ownership of complex block- or subsystem-level verification problems appropriate for a Staff / T4 role.
• Strong protocol knowledge in CXL and at least one of CHI, ACE, AXI, or similar high-performance interconnect standards.
• Strong hands-on experience with SystemVerilog and UVM-based verification, including building reusable verification infrastructure for complex hardware subsystems.
• Strong understanding of cache-coherent systems, on-chip interconnects, memory-subsystem behavior, and verification of ordering and flow-control semantics.
• Experience creating test plans, assertions, coverage models, scoreboards, and debug workflows for complex hardware subsystems.
• Strong debugging skills with the ability to root-cause issues across specification, RTL, and testbench layers.
• Strong scripting and automation skills in Python or similar languages.
• Strong communication skills and the ability to work effectively across architecture, RTL, and verification teams in a fast-moving environment.

Preferred Qualifications

• Direct experience verifying coherent interconnect, cache, or memory-subsystem IP in high-performance SoCs.
• Experience with protocol-conversion or bridge-heavy subsystems, especially where CXL protocol behavior or adaptation is a major part of system validation.
• Experience with formal verification, performance-oriented verification, or emulation / FPGA-assisted debug.
• Experience mentoring other engineers and influencing verification quality beyond immediate ownership scope.
• Familiarity with large subsystem integration challenges involving coherent traffic, ordering, arbitration, QoS, and error handling across multiple interface types.

What Success Looks Like

• Verification plans are complete, concrete, and aligned to the real architectural risks.
• Critical bugs are found early, reproduced efficiently, and closed with durable fixes.
• Coverage and test quality improve meaningfully under your ownership.
• The coherent interconnect verification effort becomes more scalable, predictable, and reusable because of your contributions.
• Design and architecture teams rely on you as a strong technical partner for difficult verification and debug problems.

Additional Information

• This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States of America.
• As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire.
• We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.