Senior ASIC Verification Engineer, Coherent High Speed Interconnect

About the role

We are seeking a Senior ASIC Verification Engineer for our Coherent High Speed Interconnect team. Our team has been pioneering visual computing for two decades, including innovations in GPU technology that power modern gaming, film production, product design, medical diagnostics, and scientific research. We are now entering a new era of AI computing, driven by GPU deep learning, which is transforming how we solve complex problems.

Responsibilities

• Verify the design and implementation of high-speed coherent interconnects for mobile SoCs and GPUs.
• Architect test bench environments for unit level verification.
• Develop verification infrastructure including Testbenches, BFMs, Checkers, and Monitors.
• Complete test/coverage plans and ensure the correctness of the design.
• Collaborate with architects, designers, emulation, and silicon verification teams.

Requirements

• Bachelor's or Master’s Degree (or equivalent experience)
• 3+ years of relevant verification experience
• Experience in architecting test bench environments for unit level verification
• Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies
• Prior Design or Verification experience of Coherent high-speed interconnects
• Knowledge of industry standard interconnect protocols like PCIE, CXL, CHI (useful)
• Strong background developing TB's from scratch using SV and UVM methodology
• C++ programming language experience, scripting ability, and expertise in System Verilog
• Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
• Strong debugging and analytical skills
• Experienced communication and interpersonal skills

Qualifications

• Bachelor's or Master’s Degree (or equivalent experience)
• 3+ years of relevant verification experience
• Experience in architecting test bench environments for unit level verification
• Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies
• Prior Design or Verification experience of Coherent high-speed interconnects
• Knowledge of industry standard interconnect protocols like PCIE, CXL, CHI (useful)
• Strong background developing TB's from scratch using SV and UVM methodology
• C++ programming language experience, scripting ability, and expertise in System Verilog
• Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
• Strong debugging and analytical skills
• Experienced communication and interpersonal skills

Skills

• System Verilog
• C++ programming language
• Scripting ability
• Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)

Benefits

• Equity
• Benefits

Pay

Base salary range: $136,000 - $218,500 for Level 3, and $168,000 - $264,500 for Level 4.

Schedule

NVIDIA is widely considered to be one of the technology world’s most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Contact

Applications for this job will be accepted at least until July 10, 2026.