Mid-level Physical Design Engineer CPU

About The Role

Join a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a Mid-level Physical Design Engineer CPU, you will contribute to delivering high-performance, power-efficient silicon using advanced process technologies. In this role, you will take on increasing ownership within the RTL-to-GDS flow, working on block-level implementation while collaborating closely with cross-functional teams. This position offers strong growth opportunities as you build depth in physical design and SoC development.

What You’ll Do

• Execute physical design implementation for CPU core blocks or subsystems
• Perform synthesis, floor planning, place and route (PnR), and design closure activities
• Conduct static timing analysis (STA), power analysis, and physical verification
• Identify and debug timing, power, and design rule violations
• Contribute to achieving timing, power, and area (PPA) targets
• Develop and maintain scripts for design automation (e.g., TCL, Python)
• Collaborate with RTL design, verification, clocking, and full-chip teams
• Support improvements to design flows, methodologies, and best practices
• Document technical work and share knowledge within the team

Behavioral Traits That We Are Looking For

• Strong analytical and problem-solving skills
• Takes ownership of assigned tasks and delivers with accountability
• Works effectively in collaborative, cross-functional environments
• Communicates technical information clearly and concisely
• Shows adaptability in a fast-paced, evolving engineering environment
• Demonstrates continuous learning and skill development

Why Join Us

Work on cutting-edge CPU core designs that power client, server, IoT, and AI platforms used worldwide. Be part of a team driving innovation at advanced semiconductor process nodes. Contribute across the full RTL-to-GDS flow, gaining exposure to complex, high-impact silicon design. Collaborate with experienced engineers across architecture, design, and full-chip integration. Grow your technical expertise through challenging problems, modern tools, and continuous learning opportunities. Join a culture that values inclusion, collaboration, and diverse perspectives while delivering industry-leading technology. Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life.

Qualifications

• Bachelor's in Computer / Electrical Engineering or related field with 5+ years of relevant work experience.
• Or a Master's in the same field with 3+ years of relevant work experience.

Your Experience Described Above Must Be In The Following:

• Industry experience/exposure with CPU Micro-Architecture
• Physical design best known practices concerning floor-planning, routing techniques, clock distribution
• Static Timing Analysis, Noise analysis, and reliability verification techniques
• RTL to GDS methodologies and formal equivalence
• Experience with one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP

Preferred Qualifications And Experience

• Experience with Synthesis of a digital logic block, which was integrated into a large SoC or IP
• Experience with Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus)