Junior Physical Design Engineer (CPU)

About The Role

Join a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a Junior Senior Physical Design Engineer (CPU), you will contribute to cutting-edge silicon design using advanced process technologies. You will work alongside experienced engineers to support implementation from RTL to GDS, gaining hands-on experience in high-performance, power-efficient processor design.

What You’ll Do

• Support physical design execution for CPU core or subsystem blocks under guidance
• Aid in synthesis, place and route (PnR), and physical verification tasks
• Perform analysis for timing, power, and design rule compliance
• Debug and resolve design issues with mentorship from senior engineers
• Contribute to script and flow development (e.g., TCL, Python)
• Collaborate with cross-functional teams including RTL design, verification, and full-chip integration
• Document design work and contribute to best practices and design flows

Behavioral Traits That We Are Looking For

• Strong learning agility and curiosity
• Pays close attention to detail and quality
• Communicates clearly and effectively in a team environment
• Demonstrates adaptability and openness to feedback
• Buils collaborative relationships across teams

Why Join Us

• Work on cutting-edge CPU core designs that power client, server, IoT, and AI platforms used worldwide
• Part of a team driving innovation at advanced semiconductor process nodes
• Contribute across the full RTL-to-GDS flow, gaining exposure to complex, high-impact silicon design
• Collaborate with experienced engineers across architecture, design, and full-chip integration
• Grow your technical expertise through challenging problems, modern tools, and continuous learning opportunities
• Join a culture that values inclusion, collaboration, and diverse perspectives while delivering industry-leading technology
• Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life

Qualifications

• Minimum Qualifications:
  • Bachelor's in Computer / Electrical Engineering or related field with 2+ years of educational or work experience.
  • Or a Master's in the same field with 3+ months of educational experience.
• Your Experience Described Above Must Be In The Following:
  • Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure
  • PV convergence (including static timing and power analysis)
  • Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks
  • Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby)
  • Experience with one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP
• Preferred Qualifications:
  • Physical design best known practices concerning floor-planning, routing techniques, clock distribution
  • Static Timing Analysis, Noise analysis, and reliability verification techniques
  • RTL to GDS methodologies and formal equivalence
  • Familiar with Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus)

Position Details

• Job Type: College Grad
• Shift: Shift 1 (United States of America)
• Primary Location: US, Oregon, Hillsboro
• Additional Locations: Business Group Intel

Annual Salary Range

$105,650.00 - 172,860.00 USD

Work Model

This role will require an on-site presence.