CPU Core Physical Design Methodology Staff Engineer

Key Responsibilities

• Design, implement, and maintain end-to-end physical implementation flows (Synthesis through Signoff) that prioritize scalability, reproducibility, and high Quality of Results (QoR).
• Act as the primary interface with EDA vendors to drive tool adoption, evaluate new features, and troubleshoot complex tool-behavior issues.
• Develop and deploy advanced scripting frameworks (Tcl/Python) to automate design space exploration, ECO implementation, and multi-corner timing closure.
• Systematically analyze and tune tool settings—including placement density, routing congestion management, and clock tree synthesis (CTS) strategies—to meet aggressive frequency and power targets.
• Build and refine automated signoff loops (STA, IR/EM, Physical Verification) to ensure high-confidence tape-outs with minimal iterations.
• Develop and validate complex SDC constraints, ensuring that tool-driven optimizations are aligned with architectural intent and physical realities.
• Utilize big-data approaches to analyze design metrics across multiple iterations, identifying trends in tool performance and implementing corrective methodology improvements.

Preferred Experience

• EDA & Methodology Expertise
• Tool Mastery: Expert-level proficiency in industry-standard physical design platforms (e.g., Synopsys Fusion Compiler/ICC2, Cadence Innovus).
• Scripting & Automation: Advanced Tcl/Python/Perl skills; proven ability to build custom tool wrappers, automated debug utilities, and flow-management scripts.
• Flow Customization: Experience in customizing tool-specific APIs to handle unique design challenges, such as custom cell integration or non-standard floorplanning requirements.
• QoR Tuning: Demonstrated success in "tuning the engine"—adjusting tool-specific switches, constraints, and optimization strategies to resolve timing, power, or congestion bottlenecks.
• Advanced Node Implementation: Deep understanding of the physical effects at 7nm/5nm/3nm nodes and how to configure EDA tools to mitigate parasitic, crosstalk, and LDE (Layout Dependent Effect) issues.
• Signoff Methodology: Mastery of the signoff ecosystem (PrimeTime SI, RedHawk-SC, Voltus, Calibre); experience in building "push-button" signoff flows that minimize manual intervention.
• Clocking & Power Flows: Expertise in configuring advanced CTS methodologies and power-aware implementation flows (e.g., UPF/CPF-driven design, multi-Vt optimization).
• Constraint Management: Deep knowledge of MMMC (Multi-Mode Multi-Corner) environments and the ability to manage complex timing exceptions in high-frequency CPU designs.

Technical Depth

• Advanced Node Implementation: Deep understanding of the physical effects at 7nm/5nm/3nm nodes and how to configure EDA tools to mitigate parasitic, crosstalk, and LDE (Layout Dependent Effect) issues.
• Signoff Methodology: Mastery of the signoff ecosystem (PrimeTime SI, RedHawk-SC, Voltus, Calibre); experience in building "push-button" signoff flows that minimize manual intervention.
• Clocking & Power Flows: Expertise in configuring advanced CTS methodologies and power-aware implementation flows (e.g., UPF/CPF-driven design, multi-Vt optimization).
• Constraint Management: Deep knowledge of MMMC (Multi-Mode Multi-Corner) environments and the ability to manage complex timing exceptions in high-frequency CPU designs.

Location

Austin, TX

Benefits

AMD benefits at a glance.