CPU Physical Design Engineer

Job Responsibilities

• Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
• Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
• Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
• Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
• Works intimately with industry EDA vendors to build and enhance tool capabilities to design a high-speed, low-power synthesizable CPU.
• Optimizes CPU design to improve product level parameters such as power, frequency, and area.
• Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications

• Bachelor’s in Computer Engineering or Electrical Engineering or related field with 2+ years of relevant work experience, or
• M.S. in Computer Engineering or Electrical Engineering or related field (or higher degree) with 1+ years of relevant work experience.
• 1+ years' experience in Synthesis of a digital logic block or partition.
• 1+ years of experience in each of the following:
• Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure.
• PV convergence (such as static timing and power analysis).
• Chip physical design verification including formal equivalence, electrical rules, DRC/LVS, and Noise flow.
• TCL Scripting.

Preferred Qualifications

• Knowledge with Physical design best known practices concerning floor-planning, routing techniques, clock distribution.
• At least 1 Completion of Tape Out on advanced technologies.
• Knowledge of Static Timing Analysis, Noise analysis, and reliability verification techniques.
• Knowledge of RTL to GDS methodologies and formal equivalence.
• Experience performing CPU level timing analysis and optimization, ensuring designs meet functional and performance requirements.
• Experience generating and verifying timing constraints while addressing timing violations at the chip or block level for CPU cores.
• Experience working closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning.

Benefits

Intel offers a comprehensive benefits package designed to support your well-being and financial security. This includes:

• Competitive pay and stock bonuses.
• Benefit programs such as health, retirement, and vacation.

Pay

The annual salary range for this role is $105,650.00 - 172,860.00 USD. Individual pay within this range is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.

Schedule

Shift 1 (United States of America)

Location

US, Texas, Austin