CPU Power-Management Design Engineer

About SiFive

The pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s compute platforms are enabling leading technology companies to innovate, optimize, and deliver advanced solutions across various markets, including AI, ML, automotive, data center, mobile, and consumer.

Job Description

The Role: SiFive is seeking hardware engineers passionate about designing industry-leading CPU and interconnect IP to drive the adoption of RISC-V in SOC designs. We are creating customizable IP and reducing time-to-market by designing hardware with the agility of software development. As a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer, you will contribute to cutting-edge RISC-V CPU and SoC IP designs.

Responsibilities

• Work with the architecture team to define power management requirements.
• Architect, design, and implement core clocking, reset, and power management solutions.
• Microarchitecture development and specification.
• Ensure knowledge is shared via clear documentation and collaborative design.
• Perform initial sandbox verification and work with the design verification team to create and execute thorough verification test plans.
• Work with a physical implementation team to implement and optimize physical design to meet frequency, area, power goals.
• Work with a software team to enable and optimise power management features.

Requirements

• 3+ years of recent industry experience in CPU and SoC clocking, reset, and power-management logic designs.
• Experience in high-performance, energy-efficient CPU and SoC designs.
• Expertise in CPU and SoC clocking, reset design, and power management, including: Reset control and design strategies, Clock distribution, dynamic clocking, clock gating, and clock boundary crossing strategies, Power state definition and management, Power Management Unit (PMU) design, Dynamic and static power reduction techniques, including retention and power-up/down sequencing, Dynamic voltage and frequency scaling (DVFS), and Di/dt mitigation strategies, Understanding of DFT, MBIST, Debug and Error handling in CPU designs, Power-aware simulation, Proficiency with hardware (RTL) design in Verilog, SystemVerilog, or VDHL, Hands-on experience with Spyglass, Attention to detail and a focus on high-quality design, Ability to work well with others and a belief that engineering is a team sport, Knowledge of at least one object-oriented and/or functional programming language, Background of successful CPU or SoC development from architecture through tapeout, BS/MS degree in EE, CE, CS or a related technical discipline, or equivalent experience.

Nice to Have

• Experience with AMBA Interconnect Protocols, such as AXI, AHB, and APB.
• Experience with AMBA Low Power Protocol Interface, including P-channel and Q-channel protocols.
• Experience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software.
• Knowledge of RISC-V architecture.
• Experience with Git/Github, Jira, Confluence.

Pay & Benefits

Pay & Benefits: Consistent with SiFive values and applicable law, we provide a competitive compensation package that includes flexible paid time off, health, vision and dental benefits, 401(k) plan, employee stock option program, and much more. The base pay range is $158,760.00-$194,040.00. In addition to base pay, this role may be eligible for variable/incentive compensation and/or equity. For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location. The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States of America. As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations. California residents: please see our job candidate notice for more information on how we handle your personal information and your privacy rights: Privacy Policy Document.