CPU Power-Management Design Engineer

About SiFive

The pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications. SiFive’s compute platforms enable leading technology companies to innovate, optimize, and deliver advanced solutions across various markets, including AI, ML, automotive, data center, mobile, and consumer.

Job Description

The Role: SiFive seeks hardware engineers passionate about designing industry-leading CPU and interconnect IP to drive RISC-V adoption across diverse applications. As a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer, you will work on customizing power management, reset, and clocking solutions for cutting-edge RISC-V CPU and SoC IP designs.

Responsibilities

• Work with the architecture team to define power management requirements.
• Architect, design, and implement core clocking, reset, and power management solutions.
• Microarchitecture development and specification.
• Ensure knowledge is shared via clear documentation and collaborative design.
• Perform initial sandbox verification and work with the design verification team to create and execute thorough verification test plans.
• Work with a physical implementation team to implement and optimize physical design to meet frequency, area, power goals.
• Work with a software team to enable and optimise power management features.

Requirements

• 3+ years of recent industry experience in CPU and SoC clocking, reset, and power-management logic designs.
• Expertise in CPU and SoC clocking, reset design, and power management, including: Reset control and design strategies, Power state definition and management, Power Management Unit (PMU) design, Dynamic voltage and frequency scaling (DVFS), Di/dt mitigation strategies, DFT, MBIST, Debug and Error handling in CPU designs, Power-aware simulation, Proficiency with hardware (RTL) design in Verilog, SystemVerilog, or VDHL, Hands-on experience with Spyglass, Attention to detail and a focus on high-quality design, Ability to work well with others and a belief that engineering is a team sport, Knowledge of at least one object-oriented and/or functional programming language, Background of successful CPU or SoC development from architecture through tapeout, BS/MS degree in EE, CE, CS or a related technical discipline, or equivalent experience.

Nice to Have

• Experience with AMBA Interconnect Protocols, such as AXI, AHB, and APB.
• Experience with AMBA Low Power Protocol Interface, including P-channel and Q-channel protocols.
• Experience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software.
• Experience with RISC-V architecture.
• Experience with Git/Github, Jira, Confluence.

Pay & Benefits

Pay & Benefits: Consistent with SiFive values and applicable law, we provide a competitive compensation package that includes flexible paid time off, health, vision and dental benefits, 401(k) plan, employee stock option program, and much more. The base pay range is $158,760.00-$194,040.00, and the role is eligible for variable/incentive compensation and equity. The company offers a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!