Sr. Manager, ATE Test Development Engineer

Job Description/Responsibilities

• Advantest V93000 (93K) ATE Test Program Development
• Develop, debug, and optimize ATE test programs on the Advantest V93000 (93K) test platform to validate FPGA functionality and performance.
• Utilize off-line tester tools and emulation environments to prepare and validate test flows before deployment on the ATE.
• Utilize efficient vector compression with multi-port vector capability for handling large pattern quantities with large vector depths.
• Own load-board/probe-card design and validation. Ensure test hardware meets performance, reliability, and cost targets.
• Test Plan Development and Implementation
• Define and execute comprehensive test plans tailored for FPGA architectures in collaboration with design, product, and DFT teams.
• Implement test methodologies to maximize coverage while optimizing cost, yield, and reliability.
• Test Pattern and Vector Setup
• Handle and manipulate industry-standard test pattern formats, including WGL, VCD, EVCD, STIL.
• Set up and validate functional, ATPG, MBIST, and high-speed loopback tests.
• Understand vector file structures, including cycle-based timing relationships, pin-level sequencing, and event-based triggers.
• Translate simulation patterns into 93K-compatible formats for FPGA functional verification.
• Debug and modify vector files directly on the ATE as needed for test pattern debug and optimization.
• Deep understanding of high-speed memory and serial interfaces such as SerDes, GDDR, and DDR test's function, purpose, and methodology.
• Utilize efficiently Advantest V93000 (93K) multi-port vectors.
• Commercial pattern conversion tool knowledge.
• Test Methods Development
• Capability of understanding and writing software routines to develop custom test methods to extend ATE’s built-in capabilities to achieve specific test functions such as burning an efuse and digital capture.
• Write C++ based custom solutions for test automation and result analysis.
• Device Characterization and Performance Validation
• Define characterization plans for complex high-power FPGA with the DFT team.
• Analyze process, voltage, and temperature (PVT) variations to assess device performance across environmental and manufacturing conditions, ensuring high-power FPGAs maintain timing, power, and functionality across all specified operating conditions.
• Define production test limits – Use characterization data to establish pass/fail criteria for high-volume manufacturing, preventing yield loss or excessive fallout by setting optimal test limits based on statistical analysis of device behavior.
• Identify performance bottlenecks, timing margin issues, and power-integrity failures through detailed characterization analysis, ATE-to-bench correlation by comparing tester results with bench validation measurements.
• Develop thermal management solution for device under test.
• Data Analysis and Yield Optimization
• ATE data processing and transformation – Extract, parse, and structure raw ATE data logs into readable formats such as Excel or SQL databases, ensuring efficient data organization for further analysis.
• Statistical analysis and data visualization – Perform statistical analysis to identify trends, outliers, and correlations, transforming raw test data into meaningful reports and visualizations enabling effective collaboration with design and product engineering teams.
• Optimize test limits, process parameters, and binning strategies for yield improvement.
• Semiconductor Manufacturing Integration
• Understand the semiconductor production flow, from wafer fabrication, wafer sort, assembly, to package-level testing. Ensure test strategies align with process variations, yield optimization, and reliability requirements across different manufacturing stages.
• Integration of test strategies with manufacturing processes – Develop ATE test methodologies that account for fab process variations, back-end packaging challenges, and final test requirements. Collaborate with wafer foundries, outsourced semiconductor assembly and test (OSAT) partners, and supply chain partners to ensure smooth new product introduction (NPI) and high-volume production ramp-up.
• Yield improvement and optimization – Analyze yield data to identify root causes of failures, implement corrective actions, and optimize test limits, process parameters, and binning strategies to improve overall production yield.
• Cost and Test Time Reduction
• Develop strategies to reduce test cost and optimize throughput without compromising quality.
• Minimize unnecessary test loops and refine test limits to improve efficiency.
• Implement parallel and multi-site testing to reduce test time.
• Package Substrate Design and Reliability
• Understand package substrate design principles, including signal integrity, power delivery, and material selection.
• Identify and mitigate issues such as crosstalk, impedance mismatches, and warpage.
• Analyze thermal characteristics (θJA, θJC), power dissipation, and cooling solutions to prevent thermal-induced failures.
• Reliability Qualification and Stress Testing
• Execute reliability stress tests such as HTOL, HAST, TC, HTS ESD/LU testing to ensure device reliability.
• Develop burn-in strategies for high-power devices BIB design, and test pattern development.
• Assess device aging, failure mechanisms, and reliability under operational stress conditions.
• Understand burn-in oven and its features/design and how they apply to high-power devices.