Senior ASIC Verification Engineer
About the role
As a senior member of our verification team, you'll understand the design & implementation with focus on Memory Management unit, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), implement test/coverage plans, and verify the correctness of the design. Collaborate with architects, designers, software engineers across sites to accomplish your goals. Plan and work on strategic direction of the methodology for the testbench with advance methodology.
Requirements
- Bachelors or Masters Degree in Electrical Engineering or Computer Science or Computer Engineering or equivalent experience
- 8+ years of relevant work or research experience
- Exposure to Computer Architecture, ASIC design and verification methodology is required
- Strong ability with SystemVerilog, C and/or C++, test planning, coverage closure, and creating reusable verification components
- Knowledgeable in constrained random testing with functional coverage and assertion-based verification
- Understanding of object oriented programming concepts
- Exposure to simulation tools like VCS, IES and debug tools like Debussy, GDB
- Strong interpersonal skills
- Good debugging and problem solving skills
Ways To Stand Out From The Crowd
- Understanding of memory subsystem micro-architecture, cache topologies and policies, memory management, interconnects, and/or arbiter designs is a huge plus
- Experience with Universal Verification Methodology (UVM), SystemVerilog checkers and scoreboards
- Assertion-based verification, Semiformal Verification (SFV)
- Perl or Python knowledge
Pay
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits.