Senior ASIC Verification Engineer

This role is onsite with an expectation that you will primarily work from an HPE office in Sunnyvale, CA. You’ll be in the office 2 days per week.

About the company

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live—from edge to cloud—so they can turn insights into outcomes at the speed required to thrive in today’s complex world.

HPE Networking is a leading provider of advanced routers and switches for the internet. We keep the world connected with speed, reliability, security, and ease of use. Within HPE Networking, the Silicon group pushes the boundaries of what is possible in a piece of silicon die. We build cutting-edge networking chips used to create our world-class routers and switches. Our culture thrives on innovation, teamwork, and customer success, offering opportunities to work on complex modules and subsystems where you can challenge yourself and grow.

Responsibilities

• Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
• Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
• Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
• Analyze simulation results using industry-leading simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and debug waveforms to validate design functionality.
• Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.

Requirements

• 10+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
• Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.
• Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
• Hands-on experience in test planning, coverage analysis, and debugging of complex SoC designs.
• Proficiency with industry-standard simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.

Preferred qualifications

• Experience verifying networking ASICs or router datapath/control blocks, such as packet processing, forwarding engines, or fabric interfaces.
• Familiarity with high-speed interconnects, buffers, or scheduling pipelines in large networking SoCs.
• Exposure to emulation environments, hardware acceleration, or traffic-model integration.
• Knowledge of coverage analytics, regression dashboards, and continuous-integration flows (e.g., Jenkins).
• Understanding of low-power (UPF) or formal verification methodologies.
• Experience with post-silicon bring-up and debug.
• Familiarity with emulation environments and debug flows.

Benefits

• Comprehensive health and wellbeing benefits supporting physical, financial, and emotional wellbeing for you and your loved ones.
• Personal and professional development programs to help you reach career goals, including opportunities to become a knowledge expert or apply skills across divisions.
• Unconditional inclusion with a culture that celebrates individual uniqueness and flexibility to manage work and personal needs.

Pay

Annual base salary range: USD 153,500 – 310,500 in California. Variable incentives may also be offered.