Senior ASIC Verification Engineer

About the role

As a senior member of our verification team, you will understand the design and implementation with a focus on the Memory Management Unit, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), implement test and coverage plans, and verify the correctness of the design. You will collaborate with architects, designers, and software engineers across sites to accomplish your goals and plan and work on the strategic direction of the methodology for the testbench with advanced methodology.

Responsibilities

• Understand the design and implementation with focus on Memory Management Unit
• Define the verification scope and develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors)
• Implement test and coverage plans
• Verify the correctness of the design
• Collaborate with architects, designers, and software engineers across sites
• Plan and work on the strategic direction of the methodology for the testbench with advanced methodology

Requirements

• Bachelor’s or Master’s Degree in Electrical Engineering, Computer Science, Computer Engineering, or equivalent experience
• 8+ years of relevant work or research experience
• Exposure to Computer Architecture, ASIC design, and verification methodology
• Strong ability with SystemVerilog, C, and/or C++
• Experience with test planning, coverage closure, and creating reusable verification components
• Knowledgeable in constrained random testing with functional coverage and assertion-based verification
• Understanding of object-oriented programming concepts
• Exposure to simulation tools like VCS, IES, and debug tools like Debussy, GDB
• Strong interpersonal skills
• Good debugging and problem-solving skills

Qualifications

• Understanding of memory subsystem micro-architecture, cache topologies and policies, memory management, interconnects, and/or arbiter designs
• Experience with Universal Verification Methodology (UVM), SystemVerilog checkers, and scoreboards
• Assertion-based verification, Semiformal Verification (SFV)
• Perl or Python knowledge

Pay

• Level 4: Base salary range of 168,000 USD – 264,500 USD
• Level 5: Base salary range of 196,000 USD – 310,500 USD
• Eligible for equity and benefits