ASIC Technical Leader - DFT - Silicon One

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

About the Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.

Your Impact

As an ASIC Technical Leader, you will sit at the forefront of networking hardware innovation, directly shaping Cisco’s industry-defining Silicon One architecture. You will drive groundbreaking Design-for-Test (DFT) strategies, bridging the gap between architecture, physical design, and post-silicon validation to ensure best-in-class quality for high-complexity ASICs. In this role, your technical leadership will directly fuel the next generation of best-of-breed routing and switching solutions deployed across global enterprises, data centers, and service providers.

Responsibilities

• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics needs of the designs.
• Responsible for development of innovative DFT IP in collaboration with multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
• Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post-silicon validation flows.
• Participate in the creation of innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving reusable test and debug strategies.
• Craft solutions and debug with minimal mentorship.

Requirements

• Bachelors + 12 years of related experience, or Masters + 8 years of related experience, or PhD + 5 years of related experience.
• Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan, and post-silicon debug.
• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime.
• Prior verification experience including System Verilog Logic Equivalency checking and validating the Test-timing of the design.

Preferred Skills

• Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification.
• DFT CAD development – Test Architecture, Methodology, and Infrastructure.
• Test Static Timing Analysis.
• Post-silicon validation using DFT patterns.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale.

Pay

The starting salary range for this position is $210,600.00 to $305,100.00 for new hires in U.S. and/or Canada locations, not including incentive compensation, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for specific locations is listed below:

• New York City Metro Area: $210,600.00 - $350,800.00
• Non-Metro New York State & Washington State: $189,300.00 - $312,200.00

For quota-based sales roles on Cisco’s sales plan, the ranges provided include base pay and sales target incentive compensation combined.

Benefits

• Medical, dental, and vision insurance.
• 401(k) plan with a Cisco matching contribution.
• Paid parental leave, short and long-term disability coverage, and basic life insurance.
• Eligibility to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
• Paid time away:
  • 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees.
  • 1 paid day off for employee’s birthday.
  • Paid year-end holiday shutdown.
  • 4 paid days off for personal wellness.
  • Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at a rate of 4.92 hours per pay period for full-time employees.
  • Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and business limitations).
  • 80 hours of sick time off provided on hire date and each January 1st thereafter, with up to 80 hours of unused sick time carried forward from one calendar year to the next.
  • Additional paid time away may be requested to deal with critical or emergency issues for family members.
  • Optional 10 paid days per full calendar year to volunteer.
• Eligibility to earn annual bonuses subject to Cisco’s policies (for non-sales roles).
• For sales roles, performance-based incentive pay split between quota and non-quota components, subject to the applicable Cisco plan.