ASIC Core DFT Technical Leader

Application window expected to close on 09/29/2026; posting may be removed earlier if the position is filled or sufficient applications are received.

About the Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises, Service Providers, the Public Sector, and Non-Profit Organizations worldwide. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy best-of-breed silicon from Top of Rack (TOR) switches through web-scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Join us to shape Cisco's groundbreaking solutions by designing, developing, and testing some of the most complex ASICs in the industry.

About the Role

As an ASIC DFT Technical Leader, you will drive the definition, architecture, and implementation of cutting-edge Design-for-Test strategies across Cisco’s groundbreaking Silicon One portfolio. You will lead cross-functional integration from early-stage design through post-silicon validation, establishing scalable test logic, reusable code, and robust verification methodologies. Bridging physical design, DV, and system validation teams, you’ll oversee complex functional areas and shape end-to-end electrical specifications for industry-defining hardware. In this high-visibility leadership role, your innovations will directly enhance design quality, yield, and time-to-market for some of the most advanced networking silicon on the planet.

Requirements

• Bachelor’s degree + 12 years of related experience, or Master’s + 8 years, or PhD + 5 years.
• Experience with JTAG protocols, Scan and BIST architectures, including memory BIST, boundary scan, and post-silicon debug.
• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent toolsets, and PrimeTime.
• Prior verification experience, including SystemVerilog Logic Equivalency checking and validating the test-timing of the design.

Preferred Skills

• Verilog design experience – developing custom DFT logic and IP integration; familiarity with functional verification.
• DFT CAD development – Test Architecture, Methodology, and Infrastructure.
• Test Static Timing Analysis.
• Post-silicon validation using DFT patterns.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across their entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. With a worldwide network of doers and experts, the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make a global impact. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Pay

The starting salary range for this position is $214,100.00 to $309,800.00 for new hires in U.S. and/or Canada locations, not including incentive compensation, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and training. Below are the full salary ranges for specific locations:

• New York City Metro Area: $214,100.00 - $356,300.00
• Non-Metro New York State & Washington State: $192,400.00 - $317,200.00

For quota-based sales roles, the ranges include base pay and sales target incentive compensation combined.

Benefits

• Medical, dental, and vision insurance.
• 401(k) plan with Cisco matching contribution.
• Paid parental leave, short- and long-term disability coverage, and basic life insurance.
• Eligibility for Cisco restricted stock units, which vest over defined periods of continued employment.
• Paid time off:
  • 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees.
  • 1 paid day off for employee’s birthday.
  • Paid year-end holiday shutdown.
  • 4 paid days off for personal wellness.
  • Non-exempt employees: 16 days of paid vacation per full calendar year, accrued at 4.92 hours per pay period.
  • Exempt employees: Flexible vacation time off with no defined limit (subject to business availability).
  • 80 hours of sick time off provided on hire date and each January 1st thereafter, with up to 80 hours of unused sick time carried forward.
  • Additional paid time away for critical or emergency family issues.
  • Optional 10 paid days per full calendar year to volunteer.
• Annual bonuses for non-sales roles, subject to Cisco’s policies.
• For sales roles: Performance-based incentive pay split between quota and non-quota components.
  • Quota-based incentive pay:
    • 0.75% of incentive target for each 1% of revenue attainment up to 50% of quota.
    • 1.5% of incentive target for each 1% of attainment between 50% and 75%.
    • 1% of incentive target for each 1% of attainment between 75% and 100%.
    • Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap.
  • Non-quota-based sales performance elements: 0% up to 125% of target.

Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.