ASIC Technical Leader - DFT - Silicon One

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

About the Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.

Your Impact

As an ASIC Technical Leader, you will sit at the forefront of networking hardware innovation, directly shaping Cisco’s industry-defining Silicon One architecture. You will drive ground breaking Design-for-Test (DFT) strategies, bridging the gap between architecture, physical design, and post-silicon validation to ensure best-in-class quality for high-complexity ASICs. In this role, your technical leadership will directly fuel the next generation of best-of-breed routing and switching solutions deployed across global enterprises, data centers, and service providers.

Responsibilities

• Implement Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics needs of the designs.
• Develop innovative DFT IP in collaboration with multi-functional teams and play a key role in full chip design integration with testability features coordinated in the RTL.
• Work closely with design, design-verification, and physical design teams to enable integration and validation of test logic in all phases of implementation and post-silicon validation flows.
• Participate in creating innovative hardware DFT and physical design aspects for new silicon device models, bare die, and stacked die, driving reusable test and debug strategies.
• Craft solutions and debug with minimal mentorship.

Requirements

• Bachelor's degree + 12 years of related experience, or Master's + 8 years of related experience, or PhD + 5 years of related experience.
• Experience with JTAG protocols, scan and BIST architectures, including memory BIST, boundary scan, and post-silicon debug.
• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent toolsets, and PrimeTime.
• Prior verification experience including SystemVerilog logic equivalency checking and validating the test-timing of the design.

Preferred Skills

• Verilog design experience – developing custom DFT logic and IP integration; familiarity with functional verification.
• DFT CAD development – test architecture, methodology, and infrastructure.
• Test static timing analysis.
• Post-silicon validation using DFT patterns.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. We work as a team, collaborating with empathy to make really big things happen on a global scale.

Pay

The starting salary range for this position is $210,600.00 to $305,100.00 for new hires in U.S. and/or Canada locations, not including incentive compensation, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training.

Full salary ranges for specific locations:

• New York City Metro Area: $210,600.00 - $350,800.00
• Non-Metro New York State & Washington State: $189,300.00 - $312,200.00

For quota-based sales roles, the ranges include base pay and sales target incentive compensation combined.

Benefits

• Medical, dental, and vision insurance.
• 401(k) plan with Cisco matching contribution.
• Paid parental leave, short and long-term disability coverage, and basic life insurance.
• Eligibility to receive grants of Cisco restricted stock units, vesting following continued employment.
• Paid time off:
  • 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees.
  • 1 paid day off for employee’s birthday.
  • Paid year-end holiday shutdown.
  • 4 paid days off for personal wellness.
  • Non-exempt employees: 16 days of paid vacation time per full calendar year, accrued at 4.92 hours per pay period.
  • Exempt employees: Flexible vacation time off with no defined limit (subject to business limitations).
  • 80 hours of sick time off provided on hire date and each January 1st thereafter, with up to 80 hours of unused sick time carried forward.
  • Additional paid time away for critical or emergency family issues.
  • Optional 10 paid days per full calendar year to volunteer.
• Eligibility for annual bonuses (non-sales roles).
• Sales roles: Performance-based incentive pay split between quota and non-quota components, subject to applicable Cisco plan.