Verification Engineer Senior

Key Responsibilities

• Define Project Specific Verification Strategy: Defines and implement scalable and reusable verification plans, test benches, and the verification environments for blocks, subsystems, and SoCs. Ensures meeting the required coverage levels and confirms to microarchitecture specifications.
• Lead Verification Execution: Create detailed test plans and drives technical reviews with design and architecture teams to validate these plans and proofs.
• Executes verification plan: Implement and run block/subsystem/cluster/soc simulation models to verify the design, analyze power and performance, and identify bugs.
• Investigate and Resolve Bugs: Replicate, root cause, and debug issues in the pre-silicon environment. Find and implement corrective measures to resolve failing tests.
• Collaborate Across Teams: Work closely with SoC architects, micro architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
• Enhance Future Verification Methodologies: Continuously improves existing functional verification infrastructure and methodologies.
• Absorb learnings: From post-silicon on the quality of validation done during pre-silicon development, update test plan for missing coverages and proliferate to future products.
• Lead and mentor others: Inspire and guide junior engineers, fostering their growth and development.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field with 8+ years of experience in ASIC/FPGA design verification, or a Master’s degree with 6+ years of experience in ASIC/FPGA design verification.
• Object-oriented programming (OOP) principles and their application in SystemVerilog UVM or other verification methodologies.
• Developing UVM and/or Formal based verification architectures and methodologies.
• Experience with industry standard protocols (AMBA AXI/AXI-S/CHI and Low-speed communication protocols (UART, SPI, I2C/I3C)).
• Familiarity with coverage-driven verification, constrained-random testing, and strong debugging skills.