Senior Verification Engineer

About the role

NVIDIA is seeking a Senior Verification Engineer to join the Display Team. The ideal candidate will be responsible for defining verification scope, developing and driving testplans, building scalable UVM-based infrastructure, and collaborating across global teams to ensure consistent display IP behavior.

Responsibilities

• Define verification scope, develop and drive testplans (functional and performance)
• Build scalable UVM-based infrastructure; leverage agentic AI to automate repetitive tasks, accelerate debug, and sharpen team efficiency
• Develop UVM testbenches and checkers; work with C/C++-based testbenches and debug reference models and designs developed in HLS
• Track metrics and drive coverage closure
• Critically reason through architectural solutions and partner with architects to develop well-crafted, silicon-proven designs
• Collaborate across NVIDIA sites globally and work closely with external partners and customers to deploy verification flows, ensure consistent display IP behavior across diverse tool stacks, and debug complex integration issues across organizational boundaries

Requirements

• BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field (or equivalent experience)
• 10+ years of relevant experience
• Strong hands-on expertise in UVM, SystemVerilog, Verilog, Python, and C/C++, with a passion for root-causing complex issues; experience with constrained-random stimulus, functional coverage, assertion-based verification, and C/C++-based testbenches — ideally on shipped silicon
• Proficiency with industry EDA tools (VCS, Verdi/Debussy, GDB) and strong software engineering practices: clean, maintainable code; version control; code review
• Domain knowledge of display pipelines: protocols (DisplayPort, HDMI, MIPI DSI/CSI), MMU interaction with ISO clients, and system low-power features (clock gating, power domains, retention, entry/exit sequences)
• Self-starter who dives into unfamiliar sub-blocks independently, communicates with clarity across time zones and organizational boundaries, and embraces agentic AI to solve daily engineering challenges and multiply team output

Qualifications

• Prior Display Unit Verification experience with familiarity in pixel processing, ISO performance testing, and HLS-based designs
• Hands-on experience verifying display protocols end-to-end, MMU/SMMU behavior under ISO traffic, and system-level low-power sequences
• Demonstrated experience shaping architectural specifications and micro-architecture decisions — not just implementing against them

Skills

• UVM, SystemVerilog, Verilog, Python, C/C++, constrained-random stimulus, functional coverage, assertion-based verification, C/C++-based testbenches
• EDA tools (VCS, Verdi/Debussy, GDB)
• Software engineering practices: clean, maintainable code; version control; code review
• Display pipelines: protocols (DisplayPort, HDMI, MIPI DSI/CSI), MMU interaction with ISO clients, and system low-power features (clock gating, power domains, retention, entry/exit sequences)
• Agentic AI for solving daily engineering challenges and increasing team output

Benefits

Base salary range: $168,000 - $264,500 for Level 4, and $196,000 - $310,500 for Level 5. Eligible for equity and benefits.

Pay

Base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Schedule

Full-time position.

Application Instructions

Applications for this job will be accepted at least until July 27, 2026. This posting is for an existing vacancy.