Staff Research Scientist, AI-Hardware Co-Design
About the role
The Algorithmic Solutions Group at Analog Devices, Inc. (ADI) is seeking a Staff Research Scientist, AI-Hardware Co-Design to architect the solutions that power the next generation of intelligent systems. This role focuses on bridging the gap between advanced AI algorithms and hardware implementation to define the optimal compute strategy.
Key Responsibilities
Strategic Problem Definition: Collaborate with business leads and domain experts to identify opportunities where intelligent systems—integrating sensing, actuation, and tightly coupled algorithms—can solve previously impossible problems. Focus on challenges that require holistic system innovation rather than just off-the-shelf components.
Research-to-Product: Lead technical execution from architectural design to validated proof-of-concept. Partner with researchers and hardware engineers to bridge the gap between abstract research ideas and deployable solutions.
Feasibility Analysis: Act as the "Physics of Compute" anchor for the research team. Use high-fidelity simulation, modeling, and proof-of-concepts to quantify the impact of memory hierarchy, dataflow, and precision on system performance—distinguishing between viable product paths and impractical research concepts.
System-Level Architecture & Co-Design: Drive the simultaneous optimization of algorithms and hardware. Treat the algorithm and the compute engine as a unified design space, adapting neural architectures to exploit specific hardware capabilities while selecting the optimal compute substrate—from ultra-low-power MCUs to custom accelerators—to meet strict power and area constraints.
Thought Leadership: Maintain a deep awareness of the evolving AI hardware and algorithm landscape. Bring the best ideas from the academic and industrial communities into ADI, mentoring junior engineers and guiding the team toward state-of-the-art compute paradigms.
The Ideal Candidate
You are a Computer Architect with a deep appreciation for AI, or an AI Researcher with a deep understanding of silicon. You think in terms of data movement, memory bandwidth, and energy-per-operation. You understand that hardware constraints shape algorithmic innovation, just as algorithmic needs must dictate architectural choices.
You hold a PhD specialized in Computer Architecture or Integrated Circuit Design for AI workloads, and have 3+ years of industry experience applying architectural principles to real-world engineering constraints.
You possess a profound understanding of how to organize computation and data. You have demonstrated this by either leading the design of complex AI SoCs, or by validating novel architectures through rigorous, cycle-accurate simulation.
You are proficient in modern frameworks (PyTorch, JAX) and capable of training or fine-tuning models to validate architectural hypotheses. You go beyond standard backbones to master the optimal mapping of computational graphs to silicon, orchestrating dataflow, tiling, and quantization (INT8, mixed-precision) to maximize arithmetic intensity within strict edge power budgets.
You possess deep expertise in hardware-aware deep learning. You are comfortable discussing Fourier transforms, noise floors, and sampling rates. You understand the intersection of classical Digital Signal Processing (DSP) and deep learning, capable of architecting systems where neural networks and traditional signal chains work in concert to extract information from noisy physical data.
You are familiar with Verilog/SystemVerilog or modern hardware construction languages (Chisel, PyMTL), even if you will not be writing production RTL daily.
You have proven silicon execution. You have successfully taped out a complex SoC or a custom AI accelerator. You understand the harsh reality of physical design—from timing closure to power delivery—and how these downstream constraints influence early-stage architectural decisions.
You have a strong publication record in top conferences and/or journals.