AI Research Engineer - Hardware Environments

Job Summary

We are seeking a skilled individual to teach AI models in our chip design work. The ideal candidate will have a strong understanding of the design flow and be able to create tasks that models can be tested against. This role involves writing hardware tasks, running models against them, analyzing results, and tuning tasks to ensure models are challenged appropriately.

Responsibilities

• Create tasks across the design flow including RTL implementation, verification, debug, constraints, lint/CDC, coverage, and other relevant areas.
• Run models against these tasks using a containerized toolchain setup and analyze the results to understand model behaviors and identify failures.
• Tune tasks to achieve the desired difficulty level and distinguish between inherent model limitations and areas that models may improve upon.
• Maintain the tooling and authoring process to ensure consistency and repeatability.

Requirements

• A degree in Electrical Engineering (EE) or Computer Engineering (CE), or equivalent hands-on experience in the field.
• Strong background in SystemVerilog/Verilog, either from a design or verification perspective.
• Fundamental knowledge of chip design concepts such as pipelines, finite state machines (FSMs), handshaking, memory management, clocking and reset mechanisms, critical path analysis (CDC), and more.
• Experience with various stages of the design flow including RTL implementation, verification, simulation tools (e.g., Verilator, VCS, Xcelium, Questa), synthesis, timing analysis, design-for-test (DFT), and debugging techniques.
• Proficiency in Linux, Git, and Docker.

Bonus Points

• Experience with computer architecture.
• Knowledge of formal verification or mutation testing.
• Understanding of physical design and power-performance-area (PPA) considerations.
• Hands-on experience with machine learning evaluation and assessment.

Qualifications

• Curiosity about how AI models operate within the context of chip design.

Skills

• SystemVerilog/Verilog programming skills.
• Experience with chip design tools and methodologies.
• Ability to analyze complex system behavior and identify patterns.
• Strong problem-solving and analytical skills.

Benefits

• Competitive compensation package including health insurance, retirement plans, and paid time off.

Pay & Schedule

• $200,000 annual salary with comprehensive benefits.

Contact Information

To apply, please send an introductory email to careers@arcverex.io along with your resume. ARCVEREX is an equal opportunity employer.