Staff Engineer, Digital ASIC Design (CONTRACT)

About the role

The role of the Staff Digital ASIC Designer offers the opportunity to work within the heart of the product development team and founders and to own the core of what will set Butterfly Network apart. This individual will design, implement, and verify digital signal processing, high speed interface, and system-on-a-chip logic for a suite of next-generation products.

Responsibilities

• Develop low-power RTL for large SoCs in an advanced node.
• Implement and optimize signal processing algorithms in RTL.
• Integrate multiple embedded processor cores into a large design.
• Develop efficient high bandwidth on chip data paths.
• Other Technology, Architecture, & Productivity duties as assigned.

Qualifications

• Bachelor's, Master's, or PhD in Electrical Engineering or Computer Engineering (or equivalent practical silicon design experience).
• 8+ years (typical Staff level) in digital IC / ASIC / SoC design with substantial hands-on RTL ownership and at least one major-IP or full-chip tapeout cycle.
• Proven ownership of a defined digital IP/subsystem from micro-architecture and RTL implementation through verification closure and tapeout support.
• Strong RTL skills in SystemVerilog/Verilog, including pipelined datapaths, control logic/state machines, and high-throughput streaming interfaces.
• Experience designing sustained high-throughput datapaths, including buffering/FIFOs, arbitration/backpressure, bandwidth budgeting, and SRAM/memory interface considerations.
• Strong understanding of silicon-level design constraints, including clock/reset architecture, CDC/RDC risk mitigation, power-aware design, and PPA tradeoffs.
• Effective collaboration with verification to drive functional closure through signoff (SV/UVM and/or Python-based frameworks such as cocotb).
• Experience building and using bit-accurate reference models (e.g., Python) to validate fixed-point behavior and enable end-to-end checking.
• Experience supporting post-silicon bring-up/debug and silicon correlation, partnering with firmware/validation to root-cause issues and deliver fixes.
• Strong cross-functional communication to close hardware–firmware interfaces (register maps, control/status paths, data-plane contracts) with systems/firmware stakeholders.

Values

Patient-Centric Innovators: Our mission is THE mission.
Empowered to Impact: Every voice matters.
One Team, One Goal: Unity fuels progress.
Growth Champions: We embrace challenges.
Action-Oriented Achievers: We follow through, every time.

Location

Butterfly offers a hybrid work model for most positions, with team members spending two or more days a week in the office. While flexibility is key, we value in-person connections that spark creativity and teamwork. Our offices are designed for collaboration, with comfortable workspaces, stocked kitchens, and opportunities to connect with peers.

Pay

Compensation is competitive and commensurate with experience.

Schedule

This is a hybrid position and will be based out of our office in either the Greater SF Bay Area or Burlington, MA.

Benefits

Butterfly offers a comprehensive benefits package, including health insurance, retirement plans, and paid time off.

Equal Opportunity Employer

Butterfly Network Inc. is an equal opportunity employer regardless of race, color, ancestry, religion, gender, national origin, sexual orientation, age, citizenship, marital status, disability or Veteran status.

Security Adherence

All employees are required to adhere to company security policies and procedures, utilize provided company assets securely, and complete all required security awareness training programs.