Sr. Principal Software Engineer

About the role

Cadence Design Systems is seeking a highly motivated hardware engineer to join the Modus R&D engineering team in the Design-For-Test (DFT) IP business unit. This role involves designing and implementing advanced DFT hardware, test fabrics, and on-chip test networks for next-generation System on Chips (SoCs).

Responsibilities

• Design and implement advanced DFT hardware, test fabrics, and on-chip test networks for SoCs.
• Contribute to the hardware and software development of industry-leading test solutions such as scan compression, hierarchical test access architectures, Logic Built-In-Self-Test (LBIST), Memory Built-In-Self-Test (MBIST), Power-On-Self-Test (POST), and In-System Test (IST).
• Support high-coverage, low-cost test strategies across complex semiconductor designs.
• Develop complex reusable IPs from architecture through delivery, including synthesis, lint, CDC/RDC, formal checks, timing closure, physical design, and signoff workflows.
• Manage internal and third-party/service IP integrations, including requirements review, interface alignment, quality checks, and delivery tracking.
• Debug complex hardware issues across RTL, verification, synthesis, timing, and integration environments.
• Create detailed documentation for architecture specs, design specs, integration guides, and verification collateral.
• Lead design reviews, architecture reviews, microarchitecture reviews, and implementation readiness reviews.
• Provide technical leadership across teams and mentor senior and junior engineers.

Requirements

• Strong background in Verilog/SystemVerilog RTL for digital hardware design and simulation.
• Hands-on coding and automation skills using SystemVerilog/Verilog, plus scripting with Perl and Python.
• Mastery of UVM and directed testbench IP verification, including test planning, coverage closure, debug, and working with verification teams to drive quality.
• Knowledge of network structures and methods for communicating data across an SoC.
• Proven experience developing complex reusable IPs from architecture through delivery.
• Strong experience with synthesis, lint, CDC/RDC, formal checks, timing closure, physical design, and signoff workflows.
• Ability to manage internal and third-party/service IP integrations, including requirements review, interface alignment, quality checks, and delivery tracking.
• Strong documentation skills for architecture specs, design specs, integration guides, and verification collateral.
• Deep understanding of digital design architecture, including subsystem integration, DFT, interconnects, memory-mapped interfaces, reset/clock architecture, and low-power design considerations.
• Strong knowledge of DFT requirements for SoCs, including scan, MBIST, LBIST, POST, IST, IJTAG, test access architecture, and design-for-testability tradeoffs.
• Experience with ISO 26262 functional safety concepts, including safety mechanisms, diagnostic coverage, safety requirements, and ASIL-oriented design flows.
• Exposure to security-aware hardware design, including secure boot concepts, access control, lifecycle management, key handling, or secure debug.
• Familiarity with Cadence flows such as Xcelium, JasperGold, Genus, Innovus, Tempus, Modus, and related signoff/debug environments.
• Prior experience with large software development projects is highly recommended.

Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of relevant experience in hardware design and test.
• Experience with Cadence tools and methodologies is preferred but not required.

Skills

• RTL Design & Verification
• Strong background in Verilog/SystemVerilog RTL for digital hardware design and simulation
• Hands-on coding and automation skills using SystemVerilog/Verilog, plus scripting with Perl and Python
• Mastery of UVM and directed testbench IP verification
• Knowledge of network structures and methods for communicating data across an SoC
• Proven experience developing complex reusable IPs from architecture through delivery
• Strong experience with synthesis, lint, CDC/RDC, formal checks, timing closure, physical design, and signoff workflows
• Ability to manage internal and third-party/service IP integrations
• Strong documentation skills for architecture specs, design specs, integration guides, and verification collateral
• Deep understanding of digital design architecture, including subsystem integration, DFT, interconnects, memory-mapped interfaces, reset/clock architecture, and low-power design considerations
• Strong knowledge of DFT requirements for SoCs, including scan, MBIST, LBIST, POST, IST, IJTAG, test access architecture, and design-for-testability tradeoffs
• Experience with ISO 26262 functional safety concepts, including safety mechanisms, diagnostic coverage, safety requirements, and ASIL-oriented design flows
• Exposure to security-aware hardware design, including secure boot concepts, access control, lifecycle management, key handling, or secure debug
• Familiarity with Cadence flows such as Xcelium, JasperGold, Genus, Innovus, Tempus, Modus, and related signoff/debug environments
• Prior experience with large software development projects is highly recommended

Benefits

• The annual salary range for California is $196,000 to $364,000.
• You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
• Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.

Pay

The annual salary range for California is $196,000 to $364,000.

Schedule

Our schedule is flexible and can accommodate remote work where possible.