Sr. Principal Digital Design Verification Lead

About the role

This role focuses on ensuring functional correctness, performance, and robustness of FPGA implementations through advanced simulation, testbench development, and verification methodologies. It supports the Core Vehicle Management Systems (CVMS) organization out of San Diego, CA.

Responsibilities

• Develop and maintain comprehensive verification environments for FPGA designs using SystemVerilog (UVM preferred)
• Create reusable, scalable testbenches for functional and performance verification
• Execute simulation-based verification using tools such as Questa/ModelSim
• Develop directed and constrained-random test cases to achieve high functional coverage
• Analyze simulation results, debug failures, and collaborate with design engineers to resolve issues
• Define and track coverage metrics (functional, code, toggle, etc.)
• Participate in design reviews and provide feedback from a verification perspective
• Support regression automation and continuous integration workflows
• Assist in hardware validation and bring-up when needed

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or another STEM field and 8 years of relevant experience; or Master's degree in Electrical Engineering, Computer Engineering, or another STEM field and 6 years of relevant experience
• 5 or more years of experience in FPGA verification
• Strong proficiency in SystemVerilog and modern verification methodologies (UVM strongly preferred)
• Hands-on experience with Questa and/or ModelSim
• Solid understanding of digital logic design, RTL (Verilog/VHDL), and FPGA architectures
• Experience writing testbenches, assertions (SVA), and coverage models
• Familiarity with scripting languages such as Python, Tcl, or Bash for automation
• Experience with version control systems (e.g., Git)
• Ability to obtain and maintain US Government Secret Clearance

Qualifications

• Strong experience with SystemVerilog-based verification environments and industry-standard simulation tools such as Questa
• Deep understanding of digital design and FPGA architectures

Skills

• SystemVerilog-based verification environments
• Industry-standard simulation tools such as Questa
• Advanced simulation techniques
• Testbench development
• Directed and constrained-random test case creation
• Coverage model definition and tracking
• Regression automation and continuous integration workflows
• Hardware validation and bring-up support

Benefits

• Relocation assistance may be available
• CLEARANCE REQUIRED FOR START: No
• CLEARANCE TYPE: Secret

Pay

$142,200.00 - $213,400.00

Schedule

Hybrid position