Sr. Design Verification Engineer - Digital

Job Summary

The Sr. Design Verification Engineer is responsible for developing and implementing verification plans for digital IP blocks, subsystems, and full integrated circuits within mixed-signal sensing products. The Sr. Design Verification Engineer will closely collaborate with system, digital & physical design, embedded firmware, analog, and cross functional teams. The role also includes technical leadership, mentoring and supervision of junior verification engineers, pre-silicon validation, and support to silicon validation, production test and application engineers.

Responsibilities

• Define, develop and optimize comprehensive verification plans and test strategies for digital IP blocks, subsystems, and full integrated circuits in mixed-signal products.
  • Work closely with design teams to understand micro-architecture and functional specifications.
  • Create and maintain detailed test plans, coverage models, and verification environments.
  • Drive coverage closure including functional, code, and assertion-based coverage.
  • Generate technical documentation and drive verification reviews.
• Design and implement UVM testbench environments using SystemVerilog for digital IP blocks, subsystems, and full-chip verification.
  • Perform block and chip-level RTL and gate-level verification of digital logic interfacing with analog peripherals via behavioral models provided by the analog team.
  • Develop constrained-random verification environments, directed test cases, and reusable verification components (drivers, monitors, scoreboards, coverage models).
  • Debug complex simulation failures and identify root causes in RTL or verification environments.
  • Improve verification scalability and reuse across projects through environment enhancement and tool automation.
  • Build and maintain regression infrastructure, continuous integration flows, and coverage tracking.
• Interface with system, digital hardware, embedded firmware, analog and cross functional teams.
• Supervise and mentor junior verification engineers.
• Drive adoption of advanced verification methodologies, best practices and tool evaluation.
• Support silicon lab evaluation, performance characterization and debug.
• Technical support to test, product and application engineers.

Minimum Qualifications

• 8+ years of industry experience in integrated circuit design verification (DV)
• In-depth knowledge and experience in digital IC verification for mixed-signal ICs with MCU based hardware systems (ARM, RISC-V, PIC, STM32) with memories, custom digital micro-architecture, interfaces, dedicated hardware peripherals, embedded signal processing, external IPs, and analog peripherals.
• Proficiency in SystemVerilog as a high-level verification language with strong UVM implementation skills, Verilog for RTL comprehension and gate-level debug, Python scripting for verification automation, and industry-leading EDA verification tools (Synopsys VCS, Cadence Xcelium, Siemens Questa).
• Experience with standard hardware protocols (I2C, I3C, SPI, MIPI).
• Strong analytical, synthesis and problem solving skills.
• Demonstration of technical leadership.
• Independent, self-motivated, rigorous, innovating, team player and able to follow through.
• Excellent verbal and written communication skills.
• B.S. or M.S. in Electrical or Computer Engineering.

Desired Qualifications

• Familiarity consuming analog behavioral models (SV-RNM, Verilog-AMS) provided by analog design teams to verify digital control logic and mixed-signal interfaces.
• Formal verification experience using JasperGold, Synopsys VC Formal, or equivalent (property checking, FSM verification, protocol compliance).
• Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) sign-off experience using SpyGlass CDC, JasperGold CDC, or equivalent.
• Low-power verification experience including UPF/CPF for power domain management — relevant for battery-powered consumer applications.
• Lint and structural sign-off experience (SpyGlass Lint or equivalent).
• Knowledge of system-level integration: digital hardware, embedded firmware, signal processing concepts.
• Experience with capacitive sensing, touch, or proximity ICs.