Sr. Physical Design Verification Engineer, Annapurna Labs

About the role

Annapurna Labs designs silicon and software that accelerates innovation. This role involves designing and optimizing semiconductor designs through physical verification processes.

Responsibilities

• Drive full chip floorplan, integration and physical verification sign-off and closure
• Define, execute and optimize next-generation physical verification and integration methodologies using industry-standard EDA tools (Calibre, IC Validator)
• Perform DRC (Design Rule Checking), LVS (Layout vs. Schematic), PERC (Programmable Electrical Rule Check) verification, and Fill insertion
• Debug and resolve physical verification issues in collaboration with layout and design teams
• Interface with foundries for MT form, rule deck updates and violation waivers
• Develop and maintain verification runsets and methodologies
• Support technology file development and qualification
• Fine tune cloud infrastructure to improve compute and storage utilization for physical design work
• Mentor junior engineers on physical verification methodologies and closure

Requirements

• Experience in Python, Perl, or another scripting language
• Bachelor's degree + 10 years or Master's degree + 7 years in EE/CS, or related field
• 5+ years in physical verification for advanced technology nodes
• Expert knowledge of industry-standard physical verification tools (Calibre, IC Validator, PVS)
• Strong understanding of semiconductor manufacturing processes and design rules
• Proven track record of successful tape-outs
• Strong communication and collaboration abilities
• Design Flow Knowledge: Understanding of backend physical design flows (FC/Innovus)

Qualifications

• Experience with integration and verification in advanced nodes [5nm or below]
• Knowledge of custom and digital design flows
• Expertise with DFM (Design for Manufacturing) methodologies
• Expertise in reliability verification (ESD, EM, IR drop)
• Background in layout design or custom IC development