Physical Design Verification Manager, Annapurna Labs

About the role

Annapurna Labs (our organization within AWS Utility Computing) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

Responsibilities

• Own end-to-end physical verification strategy for AWS's most complex SoCs (≥100M gates), from floorplan to tape-out
• Define verification closure roadmap, resource allocation, and risk-mitigation plans for concurrent projects
• Standardize industry-leading verification methodologies (Calibre, IC Validator, PVS) across the organization
• Drive automation of runsets, reporting, and debug flows using Python/Perl scripts; reduce manual effort by ≥40%
• Lead a team of 3–5 Sr. PDV Engineers, setting goals, conducting quarterly reviews, and career-pathing
• Mentor junior engineers on advanced-node debug techniques, DFM, and reliability verification (IR drop, EM)
• Pilot next-gen verification technologies (e.g., AI-driven DRC, parallel cloud-based LVS) to stay ahead of 5nm/3nm node complexities

Requirements

• BS + 10 yrs or MS + 9 yrs in EE, CS, or related field
• 8+ years in physical verification, 5+ years managing engineers or budgets
• Expertise in Calibre, IC Validator, or PVS
• Experience in scripting languages such as Perl, Python, or Tcl
• Experience building high-performing teams and aligning cross-functional priorities

Qualifications

• Advanced-node expertise: 5nm, 4nm, or N4P experience—especially with AWS/N4P designs
• DFM & Reliability: Deep knowledge of IR drop, EM, ESD, and parametric yield analysis
• Publishations: Technical papers or presentations at DAC, ISSCC, or internal AWS forums