Sr. Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning

About the role

AWS Utility Computing (UC) provides product innovations — from foundational services such as Amazon’s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS’s services and features apart in the industry. As a member of the UC organization, you’ll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services.

Responsibilities

• Develop & maintain flows for block and full-chip level static timing analysis
• Write, debug & validate timing constraints for blocks and full-chip
• Run Static Timing Analysis and give frequent feedback to team members and leads
• Provide guidance on how to fix timing issues (generate ECOs, fix constraint issues)
• Develop scripts to automate running timing analysis and generate reports
• Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch teams

Requirements

• Experience in scripting languages such as Perl, Python, or Javascript
• BS + 8yrs or MS + 6yrs or PhD + 4yr in EE/CS
• Expertise in timing analysis fundamentals
• 3+ years doing Static Timing Analysis
• 3+ years with timing constraint development
• Understanding of ASIC Physical Design from RTL-to-GDSII
• Understanding of other sign-off activities (ir/em, physical verification, DFT)

Qualifications

• Expertise in STA tools (examples: PrimeTime, Tempus or others)
• Experience in ECO flows (examples: PT-DMSA, Tempus-ECO, Tweaker or others)
• Experience in advanced nodes - 16nm or below
• Expertise in parasitic extraction tools (examples: STAR-RC, Quantus or others)
• Experience with circuit level analysis using tools like SPICE / SPECTRE
• Experience with timing of IO interfaces like DDR, HBM, PCIe, Die-to-Die etc.

Skills

• Mentoring, leading and coaching
• Developing flows using STA tools (examples: PrimeTime, Tempus or others)
• ECO flows (examples: PT-DMSA, Tempus-ECO, Tweaker or others)
• Advanced nodes - 16nm or below
• Parasitic extraction tools (examples: STAR-RC, Quantus or others)
• Circuit level analysis using tools like SPICE / SPECTRE
• Timing of IO interfaces like DDR, HBM, PCIe, Die-to-Die etc.

Benefits

Work/Life Balance: We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why we strive for flexibility as part of our working culture.

Pay

$183,000.00 - $247,600.00 USD annually

Schedule

N/A