Sr. FPGA Engineer

What You’ll Do

• FPGA Architecture Ownership: Define and specify hardware architecture for high-dynamic acquisition, tracking, data decoding, and measurement processing pipelines.
• DSP/FPGA Implementation: Lead fixed-point design, resource budgeting, and pipeline optimization to achieve performance and latency targets.
• Technical Leadership: Establish RTL best practices and guide junior engineers through complex design cycles and hardware validation phases.
• Cross-Functional Integration & HW/SW Partitioning: Define and optimize HW/SW partitioning in collaboration with SW teams; ensure efficient SW interfaces, seamless integration, robust system-level testing, and preservation of performance margins.
• Performance & Risk Management: Drive timing closure, power optimization, and system-level performance verification; resolve complex cross-domain issues.
• Vendor & IP Integration: Evaluate and integrate third-party IP cores, define acceptance criteria and compliance testing.
• Verification Strategy: Establish robust verification frameworks, including simulation, emulation, and hardware validation.

What You’ll Bring

• PhD or MS/BS in EE/CE or related field, 7+ years of FPGA and DSP implementation experience.
• Demonstrated ownership of complex FPGA signal-processing systems from architecture to hardware validation.
• Deep expertise in fixed-point DSP implementation, pipelining, and resource optimization.
• Strong experience with high-speed interfaces and complex FPGA subsystems.
• Expert proficiency with FPGA toolchains, static timing analysis, and on-chip debugging.

Preferred Qualifications

• Experience with satellite communications, esp. with GNSS receivers and in spread-spectrum systems.
• Familiarity with processing of satellite-related measurements (code/carrier/Doppler/CN0, PRs, DRs).
• Experience supporting HIL and over-the-air validation environments.

Key Competencies

• Strong DSP foundation with practical FPGA implementation expertise.
• Execution-focused mindset with emphasis on timing closure and hardware validation.
• Clear technical communication and documentation.
• Ability to collaborate across systems, RF, software, and navigation teams to deliver flight-ready FPGA solutions.