Sr. Engineer, CPU RTL Design

About the role

We are looking for a talented engineer to join our CPU design team to define and implement RTL for high-performance CPUs. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role.

Responsibilities

• Own RTL design and microarchitecture development for a portion of a CPU block of a high-performance RISC-V CPU.
• Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and power goals.
• Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results.
• Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
• Enhance RTL design environment, tools, and methodologies to improve development efficiency.

Requirements

• Experienced in CPU microarchitecture with expertise in Rename, Scheduler, ROB, Load Store, Branch Prediction, Cache or Datapath.
• Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.
• Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.
• Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.

What You Will Learn

• End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
• Hands-on experience optimizing high performance CPU designs in both pre-silicon and post-silicon phases.
• Integration of open-source and industry-standard tools to improve RTL flows and results.
• Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.

Pay

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.