Senior CPU RTL Design Engineer

About the role

As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL) code and simulation for the CPU, enabling creation of cell libraries, functional units, and CPU IP blocks for integration into full-chip designs. Your expertise will be pivotal in defining architecture and microarchitecture features, ensuring Intel continues to deliver innovative solutions that lead the industry in performance, energy efficiency, and design integrity. By contributing to the development and optimization of logic structures, you will help create technology that enriches the lives of every person on Earth, while enabling Intel to achieve its broader mission of engineering a brighter future.

Responsibilities

• Develop and optimize logic design, register transfer level (RTL) coding, and simulation for the CPU.
• Participate in defining the architecture and microarchitecture features of the CPU design.
• Write RTL and optimize logic for power, performance, area, and timing goals.
• Ensure design integrity for physical implementation through effective strategies, tools, and methods.
• Review verification plans to ensure design features are correctly validated and resolve failing RTL tests.
• Document microarchitectural specifications (MAS) for the CPU features.
• Collaborate with SoC customers to ensure seamless integration and high-quality performance of the CPU block.

Skills

• Strong ownership of complex technical deliverables and a commitment to delivering results.
• Strong problem-solving and analytical skills with a data-driven approach.
• Excellent collaboration skills across architecture, design, verification, and integration teams.

Qualifications

Minimum qualifications:

• Bachelor's degree in electrical engineering, computer engineering, or computer science with 5+ years of relevant experience.
• Or a Master's degree in the same field with 3+ years of experience.
• 5+ years experience in CPU RTL design using System Verilog, with strong knowledge of logic design, simulation, and debug.
• 3+ years experience with modern energy-efficient and low-power logic design methods, including techniques applicable to high-frequency optimization.
• 3+ years experience in cross‑clock domain crossings and power‑aware design.
• 3+ years experience in scripting languages such as TCL, Perl, or Python.

Preferred qualifications:

• Knowledge on CPU power‑management namely power/electrical budgeting, dynamic voltage and frequency scaling, thermal, P/C states and reset sequence handling.
• Comprehensive knowledge of Intel Architecture ISA and system architecture, including x86 assembly language.
• Experience with high‑speed circuit design and optimization, specifically for datapath, circuits, and arrays.
• Familiarity with circuit planning and timing convergence processes.
• Ability to leverage broad understanding of CPU architecture to deliver impactful solutions.
• Proficient with static timing analysis, UPF and lint checks.

Benefits

Intel invests in our people and offers a complete and competitive package of benefits for employees and their families through every stage of life. The total compensation package ranks among the best in the industry, consisting of competitive pay, stock bonuses, and benefit programs that include health, retirement, and vacation.

Pay

Annual Salary Range for jobs which could be performed in the US: $141,910.00 - 269,100.00 USD. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Schedule

Job Type: Experienced Hire. Shift: Shift 1 (United States of America). Primary Location: US, Texas, Austin. Additional Locations: US, Arizona, Phoenix. Work Model: Hybrid – eligible to split time between on‑site at the assigned Intel site and off‑site. (Job posting details such as work model, location or time type are subject to change.)