Senior CPU RTL Design Engineer

About the role

Join Intel's CPU Design Team and help shape the future of energy-efficient, high-performance computing. As a Senior CPU RTL Design Engineer, you will define, develop, and optimize key microarchitectural features that power Intel's next-generation processors. This role offers the opportunity to solve complex technical challenges, influence CPU design decisions, and contribute to products that impact millions of users worldwide.

Responsibilities

• Develop and optimize logic design, register transfer level (RTL) coding, and simulation for the CPU.
• Participate in defining the architecture and microarchitecture features of the CPU design.
• Write RTL and optimize logic for power, performance, area, and timing goals.
• Ensure design integrity for physical implementation through effective strategies, tools, and methods.
• Review verification plans to ensure design features are correctly validated and resolve failing RTL tests.
• Document microarchitectural specifications (MAS) for the CPU features.
• Collaborate with SoC customers to ensure seamless integration and high-quality performance of the CPU block.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• Bachelor's degree in Electrical/Computer Engineering, Computer Science, or related STEM degree with 7+ years of relevant experience. Or a Master's degree in the same field with 5+ years of experience.
• 7+ years of experience in RTL design using System Verilog, with strong knowledge of hardware modeling and logic debug environments.
• 5+ years of experience with energy-efficient and low-power logic design methods, including techniques applicable to high-frequency optimization.
• 5+ years of experience in Clock-domain crossing (CDC) and Power-aware design.
• 3+ years of experience in scripting languages such as TCL, Perl, or Python.

Preferred Qualifications

• A PhD in the same fields with 2+ years of experience.
• Knowledge of CPU power-management, namely power/electrical budgeting, dynamic voltage and frequency scaling, thermal, P/C states, and reset sequence handling.
• Comprehensive knowledge of Intel Architecture ISA and system architecture, including x86 assembly language.
• Experience with high-speed circuit design and optimization, specifically for datapath, circuits, and arrays.
• Familiarity with circuit planning and timing convergence processes.
• Ability to leverage broad understanding of CPU architecture to deliver impactful solutions.
• Proficiency with static timing analysis, UPF, and lint checks.

Behavioral Traits

• Strong Ownership: Takes responsibility for complex technical deliverables and drives issues to closure.
• Technical Curiosity: Continuously seeks deeper understanding of architecture, design tradeoffs, and emerging technologies.
• Bias for Action: Identifies issues early and proactively develops solutions.
• Collaboration: Works effectively across architecture, verification, physical design, SoC integration, methodology, and validation teams.
• Communication: Clearly communicates technical concepts, design decisions, and tradeoffs, while fostering effective collaboration across cross-functional engineering teams.
• Critical Thinking: Uses data and engineering rigor to evaluate alternatives and make decisions.
• Continuous Improvement: Looks for opportunities to improve design quality, efficiency, methodologies, and development processes.
• Influence Without Authority: Builds alignment and drives technical decisions through expertise and collaboration.

Benefits

Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life. This includes health, retirement, and vacation benefits, as well as stock bonuses.

Pay

Annual Salary Range for jobs which could be performed in the US: $141,910.00 - $269,100.00 USD. The range displayed reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.

Schedule

This role will be eligible for Intel’s hybrid work model, which allows employees to split their time between working on-site at their assigned Intel site and off-site.