CPU RTL Design Engineer

About the role

The Role And Impact: As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL) code and simulation for the CPU, enabling creation of cell libraries, functional units, and CPU IP blocks for integration into full-chip designs. Your expertise will be pivotal in defining architecture and microarchitecture features, ensuring Intel continues to deliver innovative solutions that lead the industry in performance, energy efficiency, and design integrity. By contributing to the development and optimization of logic structures, you will help create technology that enriches the lives of every person on Earth, while enabling Intel to achieve its broader mission of engineering a brighter future.

Key Responsibilities

• Develop and optimize logic design, register transfer level (RTL) coding, and simulation for the CPU.
• Participate in defining the architecture and microarchitecture features of the CPU design.
• Write RTL and optimize logic for power, performance, area, and timing goals.
• Ensure design integrity for physical implementation through effective strategies, tools, and methods.
• Review verification plans to ensure design features are correctly validated and resolve failing RTL tests.
• Document microarchitectural specifications (MAS) for the CPU features.
• Collaborate with SoC customers to ensure seamless integration and high-quality performance of the CPU block.

Qualifications

• Minimum Qualifications: Bachelor's degree in electrical engineering, computer engineering, or computer science with 7+ years of relevant experience; OR Master's degree with 5+ years of experience; OR PhD with 2+ years of experience.
• Experience: 7+ years experience in RTL design using Verilog, V2K, or System Verilog, with strong knowledge of hardware modeling and logic debug environments.
• Energy-efficient and low-power logic design: 5+ years experience with modern energy-efficient and low-power logic design methods, including techniques applicable to high-frequency optimization.
• Power-aware design: 5+ years experience in Cross-clock domain crossings and power aware design.
• Scripting languages: 3+ years experience in scripting languages such as TCL, Perl, or Python.

Preferred Qualifications

• Knowledge on CPU power-management: Knowledge on CPU power-management namely power/electrical budgeting, dynamic voltage and frequency scaling, thermal, P/C states and reset sequence handling.
• Intel Architecture ISA and system architecture: Comprehensive knowledge of Intel Architecture ISA and system architecture, including x86 assembly language.
• Circuit design: Experience with high-speed circuit design and optimization, specifically for datapath, circuits, and arrays.
• Circuit planning and timing convergence: Familiarity with circuit planning and timing convergence processes.
• Communication skills: Ability to leverage broad understanding of CPU architecture to deliver impactful solutions.
• Static timing analysis: Proficient with static timing analysis, UPF and lint checks.

Pay

$141,910.00 - 269,100.00 USD

Schedule

Shift 1 (United States of America)

Location

US, Texas, Austin

Additional Locations

• US, Arizona, Phoenix