Sr. ATE Test Engineer

Ferric is a technology startup based in New York City that is pioneering an entirely new approach to power delivery for Integrated Circuits and Electronic Assemblies. This approach leverages Ferric’s integration of thin-film magnetic inductors with CMOS technology to enable a significant improvement in the integration density and efficiency of voltage regulators (VRs) compared with current commercially available technologies.

About the role

As a Ferric IC Test Engineer, you will gain exposure to the full product-life of Ferric’s ICs by working with a diverse cross-functional team including IC designers, test & application engineers, engineering vendors, the fab, and our customers. The position requires a strong background in mixed-signal IC testing, experience with ATE programming and standard circuit test lab equipment, object-oriented programming, and data-analysis skills. Applicants should be self-motivating and possess excellent problem-solving and analytical skills, as well as excellent oral and written communication skills with the ability to work well and contribute on a team.

Responsibilities

• Work with IC design and test teams to create and review test plans and test cases, including providing recommendations for DFT & TFQ, test & debug visibility, etc.
• Design and development of ATE HW.
• Develop ATE test program of KGD, and package level testing of Ferric’s PMIC devices.
• Support and execute product qualification.
• Bench-level testing, characterization, and debug of full ICs and IC sub-systems as required.
• Drive engineering vendors for IC product qualification and production testing, including coordination of bench- & wafer-level tests, yield improvement, and test cost reductions.
• Interface with customers to review IC test measurement data and procedures.
• Assist with failure and root cause analysis.

Requirements

• Bachelor’s or Master’s Degree in EE.
• 3+ years ATE experience.
• Solid knowledge of ATE test program development, and equipment such as Agilent 93K and testing of Power Management IC’s.
• KGD testing experience.
• Experience executing qualification plan.
• Self-motivated, possessing a willingness to learn and grow with the position, and able to take on full ownership of finding engineering solutions.
• Excellent communication skills and effectively able to share information with others, including Ferric customers.
• Strong problem-solving skills, with solid understanding of mixed-signal IC design and test.
• Strong desire to grow and take on new challenges.
• Python programming experience.
• Lab experience with the following equipment: Oscilloscope, Digital Multimeter (DMM), Source Measure Unit (SMU), DC Power Supply Unit (PSU), Electronic Load, Spectrum Analyzer, Opal Kelly, etc.
• Knowledge of DC-DC power-converters/regulators (Buck, Boost, LDO, etc).
• Experience with PCB design and assembly, including component selection, soldering, etc.

Preferred Skills

• Master’s Degree in EE.
• Experience with statistical data analysis of IC production data, including parametric correlation analysis, yield, and quality improvement, etc.

Location

Silicon Valley, CA

Pay

$135K–170K + competitive equity offering and comprehensive benefits package.