Silicon Engineering Intern, PhD, Summer 2027

About the role

The Google Cloud and AI Infrastructure team focuses on building Google's next-generation systems. The team's work is grounded in creating custom hardware, and as an intern you'll get to collaborate with engineers from various parts of the organization to influence the future of Google Cloud and the AI infrastructure by working on the foundational technology that makes it all possible. This is the hardware that powers everything from Google Cloud, to our most advanced models like Gemini. As an intern, you will work on fundamental problems at the intersection of hardware, software, and algorithms. You will collaborate with exceptional engineers and researchers on projects that directly impact Google's custom silicon portfolio, including highly specialized AI accelerators like our Tensor Processing Units (TPUs), and complex Systems-on-a-Chip (SoCs). Your responsibilities and projects will be tailored to your expertise and could focus on any part of the system stack.

Responsibilities

Responsibilities and detailed projects will be determined based on your educational background, interest, and skills.

Requirements

• Currently pursuing a PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Project or coursework experience in any one of the silicon engineering areas: architecture and RTL, verification and validation, physical design and circuits, systems, test and CAD.
• Experience with scripting and programming languages such as Python, Tcl, Perl, or C++.
• Located in the United States for the duration of the internship program.
• Intended for students in their penultimate academic year pursuing a PhD.
• English proficiency required.
• Ability to provide an updated CV/resume and a current unofficial or official transcript in English.
• Preferred working locations: Sunnyvale, CA, USA; Austin, TX, USA; Madison, WI, USA.

Qualifications

• Currently attending a degree program in the US and available to work full time for 12 weeks outside of university terms, and also in penultimate academic year or returning to a degree program after completion of the internship.
• Research experience in specialized areas such as high-performance/low-power architectures, domain-specific accelerators (DSAs/TPUs), memory hierarchies, coherent interconnects (e.g., CXL, PCIe, UCIe, NoC), or advanced packaging/chiplets.
• Experience developing and maintaining CAD/EDA design flows, methodology infrastructure, or applying ML for chip design automation.
• Understanding of advanced ML/DL model architectures (e.g., Transformers, LLMs) with experience in performance modeling, cycle-accurate simulation, or custom AI accelerator evaluation.
• Familiarity with industry-standard EDA tools (e.g., from Synopsys, Cadence, Siemens EDA, or emulation/formal platforms).
• Demonstrated research track record and ability to work on complex, open-ended problems, with publications in conferences (e.g., ISCA, MICRO, HPCA, ASPLOS, DAC, ICCAD, ISSCC, NeurIPS, MLSys).

Pay

US: $110000 - $147000 (USD) + 0% bonus target