Silicon Engineering Intern, PhD, Summer 2027

About the role

The Google Cloud and AI Infrastructure team builds Google’s next‑generation systems, creating custom hardware that powers Google Cloud, large AI models such as Gemini, and specialized accelerators like Tensor Processing Units (TPUs). As a 12‑week intern you will work on fundamental problems at the intersection of hardware, software, and algorithms, collaborating with engineers and researchers on projects that impact Google’s custom silicon portfolio and complex Systems‑on‑Chip (SoCs).

Eligibility

• Must be located in the United States for the duration of the internship.
• Open to students in their penultimate academic year pursuing a PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• English proficiency is required for global collaboration.
• Available to work full‑time for 12 weeks outside of university terms.
• Preferred work locations: Sunnyvale, CA; Austin, TX; Madison, WI.

Minimum qualifications

• Currently pursuing a PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Project or coursework experience in at least one silicon‑engineering area (e.g., architecture and RTL, verification and validation, physical design and circuits, systems, test and CAD).
• Experience with scripting or programming languages such as Python, Tcl, Perl, or C++.

Preferred qualifications

• Research experience in high‑performance/low‑power architectures, domain‑specific accelerators (DSAs/TPUs), memory hierarchies, coherent interconnects (e.g., CXL, PCIe, UCIe, NoC), or advanced packaging/chiplets.
• Experience developing or maintaining CAD/EDA design flows, methodology infrastructure, or applying machine learning to chip‑design automation.
• Understanding of advanced ML/DL model architectures (e.g., Transformers, LLMs) with experience in performance modeling, cycle‑accurate simulation, or custom AI accelerator evaluation.
• Familiarity with industry‑standard EDA tools from Synopsys, Cadence, Siemens EDA, or emulation/formal platforms.
• Demonstrated research track record with publications in top conferences (e.g., ISCA, MICRO, HPCA, ASPLOS, DAC, ICCAD, ISSCC, NeurIPS, MLSys).

Application process

Complete your application by February 26 2027. Applications are reviewed on a rolling basis; early submission is encouraged. If you have not heard back within three months, the role has likely been filled. Required materials (PDF preferred): an updated CV or resume (including anticipated graduation date in MM/YY) and a current unofficial or official transcript in English. Upload the resume in the “Resume Section” and the transcript in the “Education Section,” selecting “Now attending” for degree status. You will also be asked to indicate your preferred work location from the options listed above.

Compensation

US base salary range: $110,000 – $147,000 (USD) plus a 0% bonus target.