Silicon Engineering Intern, BS/MS, Summer 2027

About the role

Google is an engineering company that hires people with a broad set of technical skills to address technology’s greatest challenges. Interns may be placed on the Cloud Chip Innovation Infrastructure team or the Platforms & Devices team, working on custom hardware that powers Google Cloud, Search, YouTube, and advanced AI models such as Gemini. The internship focuses on silicon engineering, spanning architecture, RTL, verification, physical design, and embedded firmware, and offers the chance to collaborate with engineers and researchers across the organization.

Responsibilities

As a Silicon Engineering Intern you will work on fundamental problems at the intersection of hardware, software, and algorithms. Your projects will be tailored to your expertise and may involve any part of the system stack, including AI accelerators (TPUs), SoCs, mixed‑signal, logic, and sensor ICs. You will collaborate with product teams to define chip requirements, develop automation scripts or CI/CD pipelines, and contribute to the silicon development process.

Qualifications

• Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Project or coursework experience in at least one Silicon Engineering area: architecture and RTL, verification and validation, physical design, circuits, systems, test, or CAD.
• Experience with scripting or programming languages such as Python, Tcl, Perl, or C++.
• U.S. residency for the duration of the internship and availability to work full‑time for 12 weeks outside of the university term.
• Penultimate academic year (or returning to a degree program after the internship).

Preferred qualifications

• Coursework, lab, or internship experience in computer architecture, digital logic/RTL design, ASIC/SoC verification (UVM/SystemVerilog), physical design, or embedded firmware.
• Experience developing automation scripts or CI/CD pipelines for hardware design and verification workflows using Python, Tcl, or Bash.
• Familiarity with FPGA prototyping platforms, lab test equipment (oscilloscopes, logic analyzers), or chip tape‑out/shuttle programs.
• Knowledge of industry‑standard EDA tools (e.g., Synopsys, Cadence, Siemens EDA) for simulation, synthesis, lint/CDC, or place‑and‑route.
• Understanding of AI/ML hardware acceleration concepts, memory hierarchies, or standard on‑chip protocols (e.g., AXI, APB, PCIe).

Skills

• Python, Tcl, Perl, C++, or Bash scripting.
• Hardware description languages (Verilog/SystemVerilog, VHDL).
• EDA toolchains for simulation, synthesis, and physical design.
• FPGA prototyping and lab instrumentation.
• Automation of design and verification flows.

Location

Preferred working locations: Sunnyvale, CA, USA; Madison, WI, USA.

Pay

US salary range: $94,000 – $125,000 (USD) plus a 0% bonus target.

Application deadline: October 9, 2026. Applications are reviewed on a rolling basis; early submission is encouraged. If you have not heard back within three months, the role may have been filled.