Senior Verification Engineer

Job Responsibility

• Pre-silicon verification of IP modules or IP subsystems
• Define and write IP verification plans based on requirements documents
• Interface with HW, FW, and SW design teams, as well as architecture and system engineering teams
• Execute verification plan according to product specification and verification requirements
• Architect, develop, debug, and run UVM based verification environment for RTL simulation
• Define and develop test cases in an appropriate verification framework
• Create stimulus and assertions, run simulation, debug test cases on design models, run regression, collect and analyze code/functional coverage

Job Qualification

• Bachelor's or Master's degree in Electrical Engineering or Computer Science with 4+ years of experience on IP/Sub-System Verification
• Proven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC
• Advanced knowledge of Verilog, System Verilog, C/C++, Shell
• High proficiency in Metric Driven Verification concepts, functional and code coverage
• High proficiency in directed and constrained random methodologies
• Good knowledge of formal verification methodologies and assertions
• Experience with debugging of designs pre- and post-silicon, in simulation and on the bench
• Excellent written and verbal communication skills
• Good knowledge in scripting languages like Perl, TCL or Python is a plus