Senior Staff System IP Design Verification Engineer

Location: Austin, TX | Full-Time | Temporary | Non-Exempt

About the Role

As a Senior Staff System IP Design Verification Contractor, you will contribute to the functional verification of System IP, including coherent interconnect and caches. This is a technical individual contributor role with heavily involved hands-on project execution. A strong background in Design Verification and hands-on experience with both block-level and top-level verification is required.

Responsibilities

• Own gate-level simulations testbench bring-up
• Own power-aware verification with UPF
• Collaborate with Physical Design teams to run and debug gate-level simulations
• Work with SoC team to debug functional fails during IP bring-up and feature execution
• Create test benches, verification environments, stimulus, and tests
• Collaborate with designers to verify the correctness of design features and resolve failures
• Develop assertions, checkers, covergroups, and SystemVerilog constraints
• Debug and root-cause functional fails from regressions
• Analyze code and functional coverage results, performing gap analysis
• Assist with silicon bring-up and root-causing failures

Requirements

• PhD, MS, or BS in Electrical or Computer Engineering
• 12+ years of industry experience in a design verification role
• Expert hands-on coding skills in testbench, stimulus, checkers development, and coverage closure
• Experience with SystemVerilog, UVM, or equivalent
• 5+ years of experience with gate-level simulations
• Knowledge of ARM protocols or equivalent (CHI, AXI, ACElite, APB)
• Experience with Git version control and Unix/Perl/Python scripting
• Good written and verbal communication skills

Pay

$85–93.00/hour

Schedule

Monday–Friday, 8:00 AM–5:00 PM

Benefits

• Medical, dental, and vision coverage
• 401(k) retirement plan
• Disability insurance