Senior PCIe IP Design Verification Engineer
About the role
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE designs, develops, manufactures, and packages Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable customers to achieve more.
As Microsoft’s cloud business grows, deploying new offerings and hardware infrastructure on time, in high volume, with high quality and lowest cost is critical. The CSME team defines and delivers operational measures of success for hardware manufacturing, improving planning, quality, delivery, scale, and sustainability related to Microsoft cloud hardware.
We are seeking a Senior PCIe IP Design Verification Engineer with a passion for customer-focused solutions and industry expertise to help envision and implement future technical solutions that optimize Cloud infrastructure.
Responsibilities
- Own or lead verification of complex Peripheral Component Interconnect Express (PCIe) Bridge IP flows.
- Learn about the design and interact with partner teams to define verification strategies and test plans.
- Develop UVM-based verification environments and run and debug simulations to drive quality.
- Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals.
- Innovate to improve verification efficiency through methodologies or tools.
- Apply industry-leading generative AI solutions to verification work.
- Share expertise and support the growth and development of others through coaching, mentorship, and collaboration.
- Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.
Qualifications
Required Qualifications:
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience.
- Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience.
- Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience.
- Equivalent experience.
Other Requirements:
- Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
- This role requires access to export-controlled information. Proof of citizenship, U.S. residency, or other protected status is required as a condition of employment.
Preferred Qualifications:
- 5+ years of pre-silicon subsystem or IP verification experience.
- 3+ years of PCIe experience.
- 7+ years of related technical engineering experience.
- Demonstrated experience verifying PCIe designs at the IP, subsystem, or SOC level.
- Experience driving IP verification for a full product cycle from definition to silicon, including writing test plans, developing tests, debugging failures, and coverage signoff.
- Hands-on technical leadership, such as creating schedules, coordinating work, driving verification closure, or solving cross-team technical problems.
- Experience with UVM, System Verilog Test Bench (SVTB), and optionally Python-based post-processing checking.
- Aptitude for scripting/software development using languages like Python.
- Experience applying generative AI to day-to-day tasks.
Pay
The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. For roles in the San Francisco Bay area and New York City metropolitan area, the range is USD $160,200 - $261,000 per year. Certain roles may be eligible for benefits and other compensation. Additional pay information can be found at Microsoft Careers Pay Information.