Senior IP Verification Engineer

About the role

This specific role will be part of a front-end multi-media IP team responsible for a varied set of multi-media focused IP's.

Responsibilities

• Participate and help drive the development of NVIDIA multi-media IP designs with emphasis on first pass success.
• Collaborate and partner with ASIC design engineers, IP architects and other verification engineers to formalize product features.
• Verify IP's using System Verilog and UVML.
• Build testbenches and enhance flows for automation of unit level trace based testing against reference C models.
• Architect and build verification architecture and associated documents.
• Develop simulation models and regression management across HLS, Verilog, and FPGA simulations.
• Perform performance testing and analysis, functional and code coverage tracking and closure.
• Help the team advance verification techniques and methodology.
• IP integration testing into full chip environment.

Requirements

• BS/MS Electrical or Computer Engineering (or equivalent experience)
• 5+ years of proven design verification experience
• Expertise in verifying sophisticated IP's with System Verilog
• Experience with verifying High-Level-Design (HLS) designs (plus)
• Programming and scripting experience with C and Python
• Familiar with using AI enabled IDE's for code development

Qualifications

• Excellent written, verbal and technical communication skills
• Demonstrate use of out-of-box thinking for creative solutions to highly sticky problems

Skills

• System Verilog
• High-Level-Design (HLS)
• Verification Architecture
• Testbenches and Automation
• Simulation Models
• Performance Testing
• Functional and Code Coverage Tracking
• Verification Techniques
• IP Integration Testing

Benefits

• Competitive salaries
• A generous benefits package

Pay

• Base salary range: $136,000 - $218,500 for Level 3, and $168,000 - $264,500 for Level 4

Schedule

• Not specified