Senior Staff Physical Design Engineer

About the role

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You have spent years in the trenches of advanced-node physical design, where a 50ps timing violation at 3nm is not an abstraction but a problem you own and solve before tapeout. The difference between a chip that works and one that doesn't often comes down to decisions you made during floorplanning or a clock-tree strategy you refined three months before signoff, and you have learned to see those moments coming. You think in flows, not just tools. When you open ICC2 or Fusion Compiler, you are not just running commands, you are building repeatable methodologies that make the next block faster, cleaner, and more predictable. Automation is not a nice-to-have for you, it is how you scale your impact across a team working on subsystems that will ship in products used by millions. Timing closure does not scare you. Neither does working with a distributed team across time zones to debug a setup violation that only shows up in one corner. You ask the right questions, you dig into the data, and you do not stop until the path is clean and the methodology is documented. At Synopsys, you will work on real silicon at the bleeding edge, with tools you already know and problems that actually matter.

Responsibilities

• Drive timing closure and signoff readiness for advanced-node designs at 5nm, 3nm, and below, working across block, subsystem, and full-chip implementations
• Develop and refine physical design methodologies and automation flows using TCL, Python, and Perl to improve design quality, turnaround time, and predictability
• Perform static timing analysis, clock-tree synthesis, and ECO implementation using PrimeTime, ICC2, Fusion Compiler, and industry-standard signoff tools
• Analyze design data and PPA trends to identify bottlenecks, optimize workflows, and inform next-generation flow development
• Collaborate with cross-functional teams including front-end design, verification, and CAD to ensure successful silicon delivery on schedule
• Contribute to AI-assisted and machine learning-driven design optimization initiatives, applying data-driven approaches to improve implementation outcomes
• Troubleshoot complex physical design challenges including congestion, power integrity, and multi-corner timing convergence, developing scalable technical solutions that can be reused across projects

Impact

• Enable faster time-to-tapeout for advanced-node designs by building automation and methodologies that reduce manual intervention and improve first-pass success rates
• Improve PPA outcomes across multiple projects by identifying