Senior Physical Design Engineer

Overview

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) delivers the core infrastructure and foundational technologies for Microsoft’s over 200 online businesses, including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Azure platform. The Compute Silicon & Manufacturing Engineering (CSME) organization designs, develops, manufactures, and packages Microsoft’s state‑of‑the‑art computer chips, notably the Azure Cobalt. The team defines and delivers operational measures of success for hardware manufacturing, improving planning, quality, delivery, scale, and sustainability for Microsoft cloud hardware.

Responsibilities

• Drive end‑to‑end execution from synthesis through place‑and‑route for large designs, completing all sign‑off stages including timing, physical verification, EMIR, formal equivalence, and low‑power verification.
• Responsible for clock construction and CTS, and drive methodology exploration to optimize SoC blocks for clock construction.
• Coordinate with CAD, RTL/Design, DFT, Architecture, Power & Performance, Technology teams and other internal/external partners.
• Implement RTL‑to‑GDS flow in the Physical Design domain.
• Influence design tools, flows, and methodologies through a data‑driven approach.
• Foster collaboration across teams with a “One Microsoft” mindset.
• Demonstrate technical expertise across various Physical Design domains and provide clear communication on project status and planning.
• Exhibit Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.

Required Qualifications

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field + 1+ year technical engineering experience, or Master’s degree in one of those fields + 4+ years experience, or Bachelor’s degree in one of those fields + 5+ years experience, or equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including Microsoft Cloud Background Check (required at hire/transfer and every two years thereafter).
• Eligibility to access export‑controlled information, with required proof of citizenship, U.S. residency, or protected status, and verification via a valid passport (or other acceptable documentation for permanent residents, refugees, asylees).

Preferred Qualifications

• BS/MS in Electrical or Computer Engineering or related degree.
• 7+ years of experience in semiconductor design.
• Strong communication, collaboration, and teamwork skills; ability to contribute to diverse and inclusive teams.
• Proven track record in Physical Design, implementing designs through synthesis, floorplanning, place‑and‑route, extraction, timing, and physical verification.
• Production silicon tape‑outs experience in advanced foundry process nodes.
• Experience in low‑power design methodology for SoC.
• Thorough understanding of SoC or subsystem trade‑offs across power, performance, and area (PPA).
• Familiarity with various high‑speed clock construction strategies.
• Technical expertise in all aspects of Physical Design, from synthesis to sign‑off (timing, physical verification, EMIR, formal equivalence, low‑power verification).
• Ownership of complete PD execution for medium to large‑size SoC blocks, hands‑on technical domain ownership as an individual contributor, and cross‑team collaboration.
• Partnering with PD flow/CAD and PD methodology teams to identify and resolve PD TFM issues.
• Strong problem‑solving and data‑analysis skills.
• Effective communication with cross‑functional teams.

Pay

The typical base pay range for this role across the U.S. is USD $119,800 – $234,700 per year. For locations in the San Francisco Bay Area and New York City metropolitan area, the base pay range is USD $160,200 – $261,000 per year. Certain roles may be eligible for additional benefits and compensation.