Senior Staff Engineer, Physical Design

About the role

Samsung’s Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL) are building a center of excellence for Intellectual Property (IP) applied to high‑performance computing devices. As a Senior Staff GPU Physical Design Engineer you will shape physical implementation and methodology innovation for high‑performance GPU and system‑level IP, driving market‑differentiating power, performance, and area (PPA) goals across Samsung’s advanced technology nodes.

Responsibilities

• Shape physical implementation and methodology innovation for high‑performance GPU and system‑level IP, influencing implementation quality, silicon readiness, and scalable execution for next‑generation GPU IPs.
• Contribute to key stages of the physical design flow—from synthesis through floorplanning, timing closure, and sign‑off—while advancing implementation strategies and scalable execution across parallel development cycles.
• Collaborate closely with hardware, advanced design technology, and system‑level teams to resolve complex implementation challenges and deliver robust, high‑quality silicon for advanced‑node designs.
• Lead full‑chip and block‑level implementation activities, including floorplanning, placement, routing, timing closure, and sign‑off for complex GPU and SoC designs.
• Develop implementation strategies to achieve market‑differentiating PPA targets, covering power optimization, congestion management, STA‑driven convergence, and reliability considerations.
• Drive methodology and flow innovation, such as automation, tool optimization, and scalable design practices, to improve implementation quality, productivity, and repeatability.
• Enable cross‑functional collaboration with architecture, RTL, advanced design technology, software, system‑level teams, and external vendors to adapt physical design flows for cutting‑edge nodes and accelerate resolution of complex implementation and tool challenges.
• Mentor junior engineers, fostering a culture of ownership, accountability, and continuous learning while staying ahead of physical design innovation for emerging GPU technologies.

Requirements

• 11+ years of experience with a Bachelor’s degree in Computer Science/Engineering, or 9+ years with a Master’s degree, or 7+ years with a Ph.D.
• 7+ years of hands‑on experience with full physical design implementation flows, including synthesis, place‑and‑route, clock‑tree synthesis (CTS), timing closure, and sign‑off.
• Strong expertise in physical design implementation for complex GPU or SoC designs, including low‑power design, physical verification (DRC/LVS), and advanced‑node challenges.
• Extensive experience with timing analysis and convergence methodologies, including STA, signal integrity, and reliability considerations.
• Proficiency with industry‑standard EDA tools (Synopsys or Cadence: ICC2/Fusion Compiler or Innovus, PrimeTime/Tempus, StarRC).
• Strong scripting and automation skills in Python, Tcl, Shell, or Perl.
• Analytical, debugging, and problem‑solving skills with a data‑driven approach for complex flow and design challenges.
• Experience leading technical initiatives, driving process and methodology innovation, and mentoring engineers.
• Excellent collaboration and communication skills, with the ability to navigate ambiguity and influence stakeholders in a fast‑paced, global team environment.

Preferred qualifications

• Experience with advanced‑node designs (≤5 nm) and high‑performance GPU or SoC programs.
• Experience with DTCO methodologies and implementation scalability challenges.

Our team

The Advanced Design Technology and Design Implementation teams enable GPU and system‑level development within Samsung SARC/ACL and the broader System LSI organization. Working at the intersection of design technology and physical implementation, the teams partner closely with Foundry from early technology exploration through the full development cycle. The group spans advanced design methodologies, GPU physical design, CAD, and DTCO, accelerating adoption of leading technology nodes and delivering optimized PPA, silicon quality, and turnaround time for next‑generation IP solutions. You will join a highly collaborative, fast‑paced environment with direct impact on consumer technologies used worldwide.

Pay

The base pay range for this role is between $180,200 and $270,400, determined by education, skills, qualifications, experience, and work location.

Benefits

• Medical, dental, and vision insurance
• Life insurance
• 401(k) retirement plan
• On‑site lunch
• Employee purchase program
• Tuition assistance (after 6 months)
• Paid time off
• Student loan repayment program
• Wellness incentives
• MBO bonus compensation (based on company, division, and individual performance)
• Potential eligibility for long‑term incentive plan and relocation assistance