Senior SoC Compute/Memory Subsystem Architect

About the role

The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems.

Responsibilities

• Define and drive the architecture of compute complexes and high-performance memory subsystems for next-generation IPU/DPU platforms.

• Optimize system-level performance, scalability, power efficiency, and programmability while ensuring seamless interaction with networking, storage, and accelerator subsystems in hyperscale environments.

• Key responsibilities include but not limited to:

  • Compute Subsystem Architecture

  • Cache Hierarchy and Coherency Architecture

  • Memory Subsystem Architecture

  • IO Memory and Virtualization Architecture (SMMU/IOMMU)

  • System-Level Integration (Compute Network Storage)

  • Power, Efficiency, and Scaling Strategy

  • Multi-generation Architecture Roadmap

  • Cross-functional Leadership

Qualifications

• Batchelor's degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study.

• 7 + years of experience in the following:

  • SoC / CPU / memory subsystem architecture

  • CPUs architecture and cache hierarchies

  • Memory subsystems (DDR/HBM, controllers, QoS)

  • Coherent/Non-Coherent interconnect architectures

• Experience in system-level performance and PPA tradeoff analysis

• Drive architecture definition from concept to silicon

Preferred Qualifications

• Post Graduate degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study

• ARM and x86 compute and memory subsystem experience, including NUMA systems, cache coherency, or large scale platform architectures

• Familiarity with IPU / SmartNIC or accelerator centric SoCs, particularly in cloud and hyperscale environments

• Experience with PCIe, CXL, and memory semantics for high performance IO

• Track record of multi generation architectural ownership and mentoring other architects

Pay

$164,470.00 - 269,100.00 USD

Schedule

Shift 1 (United States of America)

Business Group

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies).