Senior SoC Compute/Memory Subsystem Architect

About The Role

The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems. We are seeking a Senior SoC Compute/Memory Subsystem Architect to define and drive the architecture of compute complexes and high-performance memory subsystems for next-generation IPU/DPU platforms.

What You’ll Do

• Define architecture for IPU compute complexes (e.g., ARM/x86 clusters), including core selection, scaling strategy, and configuration tradeoffs

• Architect compute subsystem roles (control plane, data plane assist, offload execution, management services)

• Drive compute architecture decisions balancing performance, power, and area

• Define and evolve multi-level cache hierarchy (private/shared caches, system-level cache)

• Architect coherency models across compute cores, accelerators, and IO subsystems (coherent vs non-coherent interactions)

• Evaluate tradeoffs between latency, bandwidth, scalability, and coherence domain complexity

• Architect system memory subsystems including: DDR/LPDDR interfaces, memory controllers and scheduling policies, bandwidth provisioning and scaling strategies

• Ensure optimal balance between latency-sensitive control workloads and bandwidth-intensive datapath workloads

• Work with Performance architect in define memory access models for compute, network, and accelerator subsystems

• Ensure seamless interaction between host, IPU/DPU compute, and offload engines

• Architect integration between: Compute subsystem, Network subsystem (packet processing pipelines), Storage and accelerator subsystems

• Optimize data movement across subsystems to minimize copies, latency, and bandwidth overhead

• Drive system architecture decisions for balanced SoC performance

• Define compute and memory strategies for power efficiency and DVFS scalability

• Architect mechanisms for: Memory bandwidth throttling / prioritization, Per-subsystem scaling

• Optimize performance-per-watt at system level

• Lead long-term roadmap for compute and memory evolution across IPU/DPU product generations

• Define scaling strategies for: Core count and frequency, Memory bandwidth and capacity, Cache scaling and topology

• Ensure backward compatibility and smooth migration across product lines

• Collaborate with teams across: Networking subsystem (NSS), SoC fabric/interconnect, Firmware, OS, and drivers, Validation and performance modeling and testing

• Drive architecture alignment and resolve cross-domain tradeoff

• Strategic thinker: Ability to define long-term architecture vision and align stakeholders

• Technical leadership: Influences across teams without direct authority

• Problem solver: Approaches complex system challenges with structured thinking

• Collaboration: Builds strong partnerships across engineering disciplines

• Customer-focused mindset: Translates real-world workload needs into solutions

• Adaptability: Navigates ambiguity and evolving technical requirements

• Ownership mindset: Drives initiatives from concept through execution

Qualifications

• Batchelor's degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study

• 7 + years of experience in the following:

  • SoC / CPU / memory subsystem architecture
  • CPU architecture and cache hierarchies
  • Memory subsystems (DDR/HBM, controllers, QoS)
  • Coherent/Non-Coherent interconnect architectures

• Experience in system-level performance and PPA tradeoff analysis

• Drive architecture definition from concept to silicon

Preferred Qualifications

• Post Graduate degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study

• ARM and x86 compute and memory subsystem experience, including NUMA systems, cache coherency, or large scale platform architectures

• Experience with IPU / SmartNIC or accelerator centric SoCs, particularly in cloud and hyperscale environments

• Familiarity with PCIe, CXL, and memory semantics for high performance IO

• Track record of multi generation architectural ownership and mentoring other architects

Pay

$164,470.00 - 269,100.00 USD

Schedule

Shift 1 (United States of America)

Location

US, California, Santa Clara

Additional Locations

• US, Arizona, Phoenix
• US, California, Folsom
• US, California, San Jose
• US, Colorado, Fort Collins
• US, Texas, Austin

Business Group

The Central Engineering Group (CEG)

Position of Trust

N/A

Intel Benefits

Intel offers a complete and competitive package of benefits employees and their families through every stage of life. See Intel Benefits for more details.

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Application Window

The application window for this job posting is expected to end by 07/31/2026

Additional Information

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.