Senior SoC Compute/Memory Subsystem Architect

About The Role

The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems. We are seeking a Senior SoC Compute/Memory Subsystem Architect to define and drive the architecture of compute complexes and high-performance memory subsystems for next-generation IPU/DPU platforms.

Responsibilities

• Define architecture for IPU compute complexes (e.g., ARM/x86 clusters), including core selection, scaling strategy, and configuration tradeoffs
• Architect compute subsystem roles (control plane, data plane assist, offload execution, management services)
• Drive compute architecture decisions balancing performance, power, and area
• Define and evolve multi-level cache hierarchy (private/shared caches, system-level cache)
• Architect coherency models across compute cores, accelerators, and IO subsystems (coherent vs non-coherent interactions)
• Evaluate tradeoffs between latency, bandwidth, scalability, and coherence domain complexity
• Architect system memory subsystems including: DDR/LPDDR interfaces, memory controllers and scheduling policies, bandwidth provisioning and scaling strategies
• Ensure optimal balance between latency-sensitive control workloads and bandwidth-intensive datapath workloads
• Work with Performance architect in define memory access models for compute, network, and accelerator subsystems
• Ensure seamless interaction between host, IPU/DPU compute, and offload engines
• Architect integration between: Compute subsystem, Network subsystem (packet processing pipelines), Storage and accelerator subsystems
• Optimize data movement across subsystems to minimize copies, latency, and bandwidth overhead
• Drive system architecture decisions for balanced SoC performance
• Define compute and memory strategies for power efficiency and DVFS scalability
• Architect mechanisms for: Memory bandwidth throttling / prioritization, Per-subsystem scaling
• Optimize performance-per-watt at system level
• Lead long-term roadmap for compute and memory evolution across IPU/DPU product generations
• Define scaling strategies for: Core count and frequency, Memory bandwidth and capacity, Cache scaling and topology
• Ensure backward compatibility and smooth migration across product lines
• Collaborate with teams across: Networking subsystem (NSS), SoC fabric/interconnect, Firmware, OS, and drivers, Validation and performance modeling and testing
• Drive architecture alignment and resolve cross-domain tradeoff

Qualifications

• Batchelor's degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study
• 7 + years of experience in the following: SoC / CPU / memory subsystem architecture, CPU architecture and cache hierarchies, Memory subsystems (DDR/HBM, controllers, QoS), Coherent/Non-Coherent interconnect architectures, Experience in system-level performance and PPA tradeoff analysis, Drive architecture definition from concept to silicon
• Post Graduate degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study
• ARM and x86 compute and memory subsystem experience, including NUMA systems, cache coherency, or large scale platform architectures
• Familiarity with IPU / SmartNIC or accelerator centric SoCs, particularly in cloud and hyperscale environments
• Familiarity with PCIe, CXL, and memory semantics for high performance IO
• Track record of multi generation architectural ownership and mentoring other architects